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In this paper, design of a novel Network on Chip (NoC) structure and its integration with Reliable Reconfigurable Real Time Operating System (R3TOS) are presented. NoC has been recently identified as a scalable communication paradigm to avoid the communication bottleneck in bus based communications. Dynamically Reconfigurable Field Programmable Gate Array (FPGA)s are particularly suited for applications...
In this paper, design of a novel reliable Application Specific Network on Chip (ASNoC) with reconfigurability and its integration with Reliable Reconfigurable Real Time Operating System (R3TOS) is presented. Network on Chip (NoC) is a well known scalable communication paradigm to avoid the communication bottleneck in bus based communications. Reconfigurable Field Programmable Gate Arrays (FPGAs) are...
In the literature, the Error Correcting Codes [ECC] are utilized in modern Communication system to make high speed data transfer over the channel and transferred data reappear reliably at the receiver end. Viterbi decoder is the best solution in maximum likelihood sense to decode for forward error correction of convolutionally encoded messages. In this paper, we have proposed radix — 4 hard decision...
In this paper, an efficient architecture called Modified Flipping is proposed. The implementation of 2 level 2D Discrete Wavelet Transform (DWT) is considered using Modified Flipping architecture. The System On Programmable Chip approach is adopted for the implementation of two level 2D DWT on Altera Field Programmable Gate Arrays based SOPC CYCLONE II EP2C35F672C6 kits with NIOS-II softcore processor...
This paper presents a novel architecture for the implementation of one level 2D DWT. The architecture is designed by using shifters and adders without using multipliers. The structure is designed for modified flipping based DWT. The System On Programmable Chip approach (SPOC) is adopted for the implementation of one level 2D DWT on Alter a Field Programmable Gate Array CYCLONE II EP2C35F672C6 kits...
Higher operating frequencies may be obtained in digital systems by using wave-pipelining which permits clock frequencies higher that dictated by largest propagation delay between input and output. This requires proper selection of clock periods and clock skews so as to latch the output of combinational logic circuits at the stable periods. Major contributions of this paper are: proposal for the implementation...
This paper presents the design and implementation of image compression using 2D DWT. Major contribution of this paper is an efficient architecture called modified flipping is proposed for the implementation of image compression using 2d DWT. The SOC approach is adopted for the implementation of 2D DWT on Altera Field Programmable Gate Arrays (FPGAs) based SOC CYCLONE II EP2C35F672C6 kits with NIOS-II...
Wave-pipelining enables a digital circuit to be operated at higher frequency. In the literature, only trial and error and manual procedures are adopted for the choice of the optimum value of clock and clock skew between the I/O registers of wave-pipelined circuits. The major contribution of this paper is the proposal for automating the above procedure for the ASIC implementation of wave-pipelined...
In the literature, pipelined systems require clock routing complexity and clock skews between different parts of the system. A circuit design technique such as wave-pipelining achieves high speed without the above limitations. Wave-pipelined circuit dispenses with the need for registers for storing the intermediate results and instead uses the inherent capacitance at the input to the various blocks...
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