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The pursuit of higher performance has driven the bus based architecture toward network-on-chip (NoC). Meanwhile the three dimensional (3D) IC technology was suggested as a promising approach to reduce the wire length since the chip size became larger and larger. Because of the trend of hundreds or even thousands of processor cores integrated on one chip, it trigged a quest for the amalgamation of...
In order to eliminate the inefficiency of the conventional bus based architecture, network-on-chip (NoC) has been suggested as a novel approach for several years. Considering the trend that hundreds or even thousands of IP blocks will be integrated on a chip, the concept of multi-cluster NoC is proposed. It usually adopts the hybrid architecture mixed with bus based local system and mesh based global...
Besides processors, DSPs and other IP blocks, Network on Chip (NoC) also integrates lots of memories. However, the research of on chip memory subsystem for NoC has not been undertaken thoroughly. In this paper, a distributed None Uniform Memory Access (NUMA) memory architecture for NoC is developed; the performance and the programming mode of this system are discussed. Two kinds of parallel algorithms...
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