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This paper presents the design and experimental test of a 40 GS/s 4 bit single-core flash ADC in a 0.13 μm SiGe BiCMOS technology. The ADC exploits a traveling-wave concept and integrates a new low-complexity Pseudo-XOR gray encoder that makes use of folded-cascode differential logic. Up to a sampling rate of 39.04 GS/s the ADC provides a measured ENOB of more than 3 bits and a SFDR of more than 24...
This paper presents a 2:1 Analog Multiplexer (AMUX) in a SiGe-HBT technology. The AMUX is used for time interleaving operation of two digital-to-analog converters (DACs) and therefore extends both the sampling rate and the bandwidth compared to a single DAC. The linear AMUX signal path allows for generation of broadband signals with higher order modulation schemes which is essential for raising data...
This paper presents a fully integrated class-A mode Differential Power Amplifier (DPA) on a thin silicon substrate intended for being embedded into flexible electronic foil systems. A high-speed and cost-effective 95 GHz-fmax, 0.25 μm SiGe:C technology (IHP process SGB25V) is used. RF performance of DPA has been evaluated with the pre- and post-thinning measurement results at die level. The behavior...
This paper presents a CMOS switching mode amplifier in a 65 nm technology with 6 V output voltage swing. Due to the low breakdown voltage of the transistors, a stacked transistor topology is proposed. Thin-oxide FETs and thick-oxide FETs are used in the output stage to increase output power and reduce circuit complexity. Driven by a continuous-wave (CW) signal the amplifier can be operated up to 3...
This paper presents a DC-coupled 27 MHz low noise amplifier (LNA) and automatic gain control (AGC) amplifier on a specially processed ultra-thin 0.5 µm CMOS gate array for the RF receiver of a wireless and bendable sensor system-in-foil. As the receiver is made for amplitude shift keying (ASK) signals, it needs an AGC. An offset feedback (OSFB) control circuit is realized to compensate for offsets...
This paper presents a 868 MHz wireless transmitter on an ultra-thin 0.5 µm CMOS gate-array for a wireless and bendable sensor-system-in-foil. Because of the technology constraints an ASK modulation is used. The simulated maximum output power is 10 dBm. The transmitter's switch-on time is very low, since this is required for the application-specific developed protocol. Thus the presented PLL has an...
A fully-differential, digital programmable gain amplifier (PGA) with a gain control range of 31 dB and step size of 1 dB is presented. The chip is fabricated in a 0.13 µm BiCMOS technology and consumes 284 mW. At a maximum gain of 25 dB, the PGA exhibits a 3-dB bandwidth of 10.1 GHz. The measured gain error for all 32 possible gain settings is between −0.19/+0.46 dB at 1 GHz. Up to 13 GHz the third...
This paper presents a 10 bit 90 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an asynchronous conversion cycle control. The asynchronous operation allows the sampling rate to be swept over a wide range. The ADC doesn't require any external reference voltages and achieves an excellent performance without the need for calibration. The comparator uses an optimized...
High speed data converters are key components for high-throughput wired, fiber optical, RF and mm-wave communication systems that apply higher order modulation formats to achieve date rates up to 100 Gbit/s and beyond. We present a 100 GS/s 8 bit 28 nm CMOS four-fold time-interleaved DAC prototype intended for coherent fiber optical links with up to 480 Gbit/s per wavelength carrier and the design...
A fully digital pulse-width pulse-position modulator (D-PWPM) is proposed that is capable of providing pulse sequences for a switching-mode power amplifier. The pulse sequences are generated according to 6-bit digital input words defining the positions of the rising and falling edges without the need for tunable analog delay cells. All possible edge positions are derived by division and phase interpolation...
An 8-bit 100-GS/s digital-to-analog converter (DAC) using a distributed output topology in 28-nm low-power CMOS for optical communications is presented. The DAC can convert 1-k symbols stored in the 1-kbyte design-for-test on-chip memory cyclically. By interleaving four 25-GS/s return-to-zero DACs, the highest signal frequency of the 100-GS/s DAC is about 25 GHz and the output image is located beyond...
This paper presents an off-line synchronization concept for the characterization of integrated circuits with receivers operating in the Gb/s range. The concept relies on the use of a programmable FPGA board with fast transmitters, a configurable delay board and an undersampling test register at the receiver side.
This paper describes the architecture and schematic design of a 4 GS/s radix-1.75 pipeline ADC in 28 nm CMOS technology. Due to large mismatch effects, a foreground calibration procedure with characterization of the transfer functions of the single pipeline stages is necessary. The gained information is used in a pure digital backend calculation. This allows increasing the effective resolution to...
This paper presents a 10 bit 12.8 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a 250 nm SiGe BiCMOS technology. An energy-efficient switching algorithm with top-plate sampling is applied which reduces the total input capacitance by 50%. High-impedance inputs with emitter followers and internal reference voltage generation make it suitable for applications...
An 8-bit 100-GS/s digital-to-analog converter (DAC) using a distributed output topology in 28-nm low-power CMOS is presented. The ENOB and SFDR ranges from 5.3 bit and 41 dB to 3.2 bit and 27 dB from DC up to 24.9 GHz at 100 GS/s. The −3dB bandwidth is larger than 10 GHz. The 100 GS/s DAC is composed of two 50 GS/s time-interleaved sub-DACs and is operated from two 25 GHz clock signals with a phase...
This paper describes a monolithic integrated singlechip transceiver intended for impulse radio (IR) — Ultra-wide Band (UWB) applications compliant to the IEEE 802.15.4a standard. The transceiver operates in the higher UWB band on the mandatory channel #9 (7.9872 GHz). The implemented nominal data rate is 850 kb/sec. The presented chip consists of the entire RF-front-end, 6bit-resolution successive...
An analog current-based 1:16-demultiplexer with integrated sample-and-hold is presented. It is designed in a 28 nm CMOS technology and is the basis for a 16-fold time-interleaved ADC. It offers sampling rates up to 64 GS/s, while consuming only 0.9 W of power and 2.6 mm2 of chip area.
High speed DACs and ADCs are key components for mm-wave communication systems that apply spectral efficient modulation formats to achieve date rates up to 100 Gbit/s. CMOS converters enable the integration with a mm-wave front-end and a high-throughput DSP on a low-cost system-on-chip. We present CMOS ADC and DAC prototypes with conversion rates up to 36 GS/s, resolutions between 3 and 6 bit and real-time...
A Viterbi Equalizer Chip (VEC) which can be applied in 40 Gb/s optical communication systems is presented. The circuit is designed and fabricated in a standard 90 nm CMOS technology with a seven metal layer stack. The internal Viterbi processing is 32 times parallelized using a sliding window decoding architecture at a clock frequency of 1.34 GHz. The VEC processes incoming samples with a resolution...
Impulse-radio ultra-wideband systems (IR-UWB) provide short-range wireless communication and precise localization simultaneously. Especially non-coherent IRUWB reduces the system complexity which enables the design of low-power receivers. This paper presents an integrating digitizer which integrates rectified baseband pulses of an IRUWB signal and provides the digitized data to the digital baseband...
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