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A novel single junction thin film solar cell structure ITO/p- a-Si:H /i1- a-Si:H/i2- μc-Si:H/n- μc-Si:H/ITO is studied with Silvaco TCAD tool in this paper. The simulation data predicts that the thickness of the maximum conversion efficiency is between 250–500nm. For the best efficiency, the intrinsic μc-Si:H layer is predicted between 1500–2500nm. The results indicate the conversion efficiency is...
In this paper we present for the first time a new GaP/a-Si:H/bulkSi solar cell. According to Silvaco TACD simulations, the GaP/a-Si:H/bulkSi solar cell has a high short-circuit current due to the downward bandgap bending. Moreover, a high doping a-Si:H can lead to a upward bandgap bending, resulting in a high open-circuit voltage. Although the GaP/a-Si:H/bulkSi solar cell has a low short-circuit current,...
In this paper, we propose a new block-oxide source/drain-tied (BOSDT) poly-Si TFT in which the additional poly-Si body (APSB) is created when the device isolation process is done after the source/drain implantation and dopant activation. For the first time, according to our results, the APSB is confirmed to have the ability to circumvent the SCEs and leakage current. Furthermore, the output characteristics...
In this work, we made a CIGS thin film solar cell with dual absorber layers which added an InGaP layer between buffer layer and CIGS layer. That is, the conventional structure of ZnO/CdS/CIGS/Mo becomes the structure of ZnO/CdS/InGaP/CIGS/Mo. And we translate the thickness and doping concentration of the additional InGaP absorber layer to find out critical parameter. Due to the presence of the additional...
In this letter, we focus on the electrical characteristics of the Partially insulating oxide Junctionless Vertical MOSFET (Piox JLVFET) and Partially insulating oxide Junction Vertical MOSFET (Piox JVFET) through computer simulations. It is clear that the PiOX JLVFET process is simple due to the absence of the source/drain (S/D) implantation and annealing, thereby reducing the fabrication cost, whereas...
This paper presents a non-classical architecture called the self-aligned bottom-gate MOSFET with edged source/drain-tie (SAESDTBG). According to the 2-D numerical simulation, the proposed structure can decrease source/drain (S/D) resistance that increases on state current (Ion). Also, it can achieve device characteristic comparable to traditional bottom-gate (TBG) MOSFET and can effectively reduce...
In this paper, we present a simulation study of short-channel characteristics of self-aligned dual-channel source/drain-tied (SA-DCSDT) MOSFETs. Two compared devices are designed, namely, the normal SA-DCSDT MOSFET and the ultimate SA-DCSDT MOSFET. According to simulation results, the DC is used to obtain a high drain saturation current, the SDT is used to get improved thermal stability, and the BOX...
In this paper, we propose a new fabrication method to form a polysilicon thin-film transistor with a smiling SiO2 layer. The experimental results suggest that the short-channel effects can be significantly reduced because the trench oxide is utilized to block the drain electric field. Furthermore, the so-called S/D tie can help to overcome the self-hating for enhancing the thermal reliability. And...
In this paper, we investigate the important device characteristics of block oxide (BO) MOSFETs (bMOS), which are the BO length (Lbo) and the height (Hbo). According to the simulation results, the variation of Lbo and Hbo strongly affects the device characteristics, such as the sub-threshold swing, threshold voltage, on-state drain current (Ion), and the off-state drain current (Ioff). This is because...
In this paper, we focus on the electrical characteristics of the partially insulating oxide (PiOX) junctionless vertical MOSFET (JLVFET) and PiOX junction vertical MOSFET (JVFET) through computer simulations. It is clear that the PiOX JLVFET process is simple due to the absence of the source/drain (S/D) implantation and annealing, thereby reducing the fabrication cost, in whereas the PiOX JVFET needs...
In this paper, we use the junctionless (JL) technology to design both JL middle-gate vertical MOS (JLMGVMOS) and JL pseudo tri-gate VMOS (JLPTGVMOS) for performance comparison on analog metrics. According to TCAD simulations, the JLPTGVMOS devices demonstrate excellent characteristics, such as high transconductance (gm), transconductance generation factor (gm/Id), and voltage gain Avi, when compared...
In this work, a qualitative comparison study of analog performance of junction and junctionless poly-Si TFTs is carefully investigated. According to numerical simulations, we find out that both gm and gD of junction poly-Si TFT are higher than the junctionless poly-Si TFT at a fixed IDS. Based on the same S/D doping concentration the junctionless poly-Si TFT can have a better short-channel behavior...
This paper presents a novel NMOS structure called two-embedded oxide (2EO) to replace the conventional PMOS transistor in a CMOS inverter. According to TCAD simulations, the 2EO is used to control the punch-through current to achieve the desired characteristics for a CMOS inverter. More importantly, compared with the conventional CMOS layout, due to the presence of two NMOS transistors to share the...
In this paper, we for the first time demonstrate a detailed radio frequency (RF) simulation study of the novel planar-type body-connected FinFET with 45 nm gate length, for which the DC behavior exhibits better ION-IOFF current ratio and improved transconductance performance when compared with a planar-type FinFET. The RF characteristics are carried out as functions of gate voltage (VG) and drain...
In this paper, we propose a novel unipolar CMOS device with embedded oxide. Good inverter and logic gate output waveforms and behaviors are obtained. Utilizing the punch through effect, the Non-Classical Unipolar CMOS is demonstrated to enhance the tPLH so that the average delay time can be improved 23% when compared with the conventional CMOS. Due to all NMOS structures are only exploited and the...
In this paper, for the first time, we demonstrate the radio frequency (RF) performance of a junctionless vertical MOSFET (JLVMOS). According to the numerical simulation results, the JLVMOS can obtain higher gm, lower gd, in comparison to a junctionless planar SOI MOSFET. This because the vertical double-gate (DG) scheme truly helps to increase the gate controllability over the channel region, resulting...
We present a non-traditional CMOS inverter composed a junctionless (JL) NMOSFET and an N+-N--P transistor which with simple process and high integration density in this paper. In the non-traditional CMOS inverter the JL NMOSFET serves as driver and the N+-N--P transistor serves as load, respectively. Based on the measurement date of the N+-N--P transistor published, we draw the load line of the non-traditional...
This paper presents a complementary Lubistor and TFET (CLTFET) inverter, which is composed of a lateral unidirectional bipolar-type insulated-gate transistor (Lubistor) load and a tunneling field effect transistor (TFET) driver. Based on the measurement data of Lubistor and TFET devices published, we have for the first time drawn the load lines and operation point line (Q line) of the new designed...
In this study, we propose a new technology to fabricate pseudo tri-gate vertical (PTGV) MOSFETs without p-n junctions, named junctionless PTGVMOS (JPTGV). According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ~ 60mV/dec, Ion/Ioff ~ 1010, and low interface trap density are all achieved. The device without p-n junctions provides an easier way for...
This work presents a preliminary performance comparison between the new and conventional block oxide (BO) bulk-MOSFETs that suggests the proposed BO structure as a candidate for scaling planar CMOS to 16 nm generation and beyond. Also, the combined application of the isolation-last process (ILP) and the BO process provides a method of forming a new BO (NBO) structure that diminishes the short-channel...
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