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In this paper, we propose a novel unipolar CMOS device with embedded oxide. Good inverter and logic gate output waveforms and behaviors are obtained. Utilizing the punch through effect, the Non-Classical Unipolar CMOS is demonstrated to enhance the tPLH so that the average delay time can be improved 23% when compared with the conventional CMOS. Due to all NMOS structures are only exploited and the...
We present a non-traditional CMOS inverter composed a junctionless (JL) NMOSFET and an N+-N--P transistor which with simple process and high integration density in this paper. In the non-traditional CMOS inverter the JL NMOSFET serves as driver and the N+-N--P transistor serves as load, respectively. Based on the measurement date of the N+-N--P transistor published, we draw the load line of the non-traditional...
This paper presents a complementary Lubistor and TFET (CLTFET) inverter, which is composed of a lateral unidirectional bipolar-type insulated-gate transistor (Lubistor) load and a tunneling field effect transistor (TFET) driver. Based on the measurement data of Lubistor and TFET devices published, we have for the first time drawn the load lines and operation point line (Q line) of the new designed...
In this paper, a novel non-classical CMOS inverter with simple process and high integration density is proposed, which is composed of a junctionless NMOSFET and a gated N--N-N+ transistor for driver and load, respectively. Also, the gated N--N-N+ transistor performance is also investigated. Based on the numerical simulations, we find out that the carrier mobility of the gated N--N-N+ transistor is...
The innovative basic punchthrough theory for the unipolar-CMOS is for the first time presented and the first unipolar-CMOS inverter has been fabricated successfully by using the 90nm technology developed in Taiwan National Nano Device Lab. The severe scaling issues with silicon can be further use and no more serious. The low-performance P-FETs can be get rid of and switch much faster both for high-electron-mobility...
To improve the bSPIFET, the SA-bSPIFET which used self-aligned process had been proposed. However there are many characteristics of bSPIFET not yet be studied. This paper focuses on the misalignment of gate shift (GS) in a 30 nm bSPIFET. Based on 2D simulation, the misalignment of GS will influence the electrical characteristics causing the degradation of the short channel behaviour and the stability...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
This work aims to examine and analyze carefully the effects of block oxide length (LBO) in a 40 nm multi-substrate-contact field-effect transistor (MSCFET). In addition, the proposed structure is based on the self-aligned (SA) gate-to-body technique. In the MSCFET design the two key parameters are the length and the height of the block oxide which are so sensitive to the short-channel effects (SCEs)...
One of the key issues that block the development of silicon-on-insulator (SOI) CMOS technology is so-called self-heating effects (SHEs). In this paper, we have investigated the electrical characteristics of multi-substrate contact field-effect transistors (MSCFETs) depend on the gate length for the first time. The proposed structure of MSCFET can significantly diminish the thermal instability occurred...
This paper presents a novel self-aligned fully depleted silicon-on-insulator field-effect transistor with block oxide (namely SA-bFDSOI) and we investigate its ultra-short channel and thermal characteristics for the first time. In the case of SA-bFDSOI, the misaligned problem caused by two different exposures via the mask in a bFDSOI can be totally overcome. Moreover, the recessed source/drain (S/D)...
For the purpose of performance improvement from bSPIFET (Si on partial insulator with block oxide field-effect transistor) technology [1], a self-aligned bSPIFET was proposed. However, a lot of electrical characteristics have not yet been studied in detail. This paper aims to investigate the device behaviour of self-aligned bSPIFET as a function of misaligned block oxide height. According to the TCAD...
In this paper, we are working on a probe into the effects of gate length (Lg) variation upon the nanoscale silicon on partial insulator field-effect transistor with block oxide (bSPIFET) being use for deca-nanometer age
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