Search results for: P K Meher

Items from 1 to 20 out of 20 results

article

A molecular tool for parentage analysis in Indian major carp, Labeo rohita (Hamilton, 1822)

L. Sahoo, P. K. Meher, K. Das Mahapatra, J. N. Saha, more

Aquaculture International > 2017 > 25 > 3 > 1159-1166

Determination of genealogical relationship between broodstock and progeny is important to estimate selection response in aquaculture breeding programs. Currently, the application of microsatellite markers for parentage determination is gaining popularity in aquaculture. In the present study, 17 simple sequence repeat markers were evaluated for parentage assignment on rohu. The allele frequencies,...

article

Preliminary genetic linkage map of Indian major carp, Labeo rohita (Hamilton 1822) based on microsatellite markers

L. Sahoo, A. Patel, B. P. Sahu, S. Mitra, more

Journal of Genetics > 2015 > 94 > 2 > 271-277

Linkage map with wide marker coverage is an essential resource for genetic improvement study for any species. Sex-averaged genetic linkage map of Labeo rohita , popularly known as ‘rohu’, widely cultured in the Indian subcontinent, was developed by placing 68 microsatellite markers generated by a simplified method. The parents and their F ₁ progeny (92 individuals) were...

article

Can microsatellite markers replace PIT tags in rohu (Labeo rohita Hamilton, 1822) selective breeding programmes?

P. K. Meher, L. Sahoo, A. Patel, P. Jayasankar, more

Journal of Applied Ichthyology > 30 > 2 > 281 - 285

This study was undertaken to assess the feasibility of microsatellite markers for resolving parentage in Labeo rohita (rohu) selective breeding programmes in lieu of conventional PIT tag marking. Ten microsatellite markers were used to assign offspring parentage. A total of 160 individuals were tested from eight full‐sibling families. Eight highly polymorphic loci with allele numbers ranging from...

article

Comparative studies on carcass characteristics of marketable size farmed mrigal Cirrhinus mrigala, (Hamilton, 1822), and silver carp Hypophthalmichthys molitrix, (Val., 1844)

B. B. Sahu, M. R. Raghunath, P. K. Meher, D. K. Senapati, more

Journal of Applied Ichthyology > 30 > 1 > 195 - 199

The carcass traits and commercial characteristics of farmed freshwater Cirrhinus mrigala and Hypophthalmichthys molitrix were investigated to calculate yield data useful for programming semi‐automated processing units. Specimens with average weights of 2500 and 3400 g were collected from both mrigal and silver carps, respectively. Samples were taken from grow‐out culture ponds of the Central Institute...

article

Carcass characteristics of marketable size farmed catla, Catla catla (Hamilton, 1822)

B. B. Sahu, M. R. Raghunath, P. K. Meher, P. C. Das, more

Journal of Applied Ichthyology > 29 > 4 > 854 - 857

The present study investigates carcass traits of farmed freshwater Catla catla for important information in calculating yield and/or providing data for programming machine/manual handling. For this purpose specimens of C. catla ranging from 1880 to 2150 g were collected from grow‐out culture ponds of the Central Institute of Freshwater Aquaculture, Odisha State, India. Carcass yield, offal yield and...

article

Carcass traits of different marketable sizes of rohu, Labeo rohita (Hamilton, 1822)

B. B. Sahu, R. Samal, P. K. Meher, P. C. Das, more

Journal of Applied Ichthyology > 29 > 3 > 673 - 677

The present study was carried out to investigate the carcass traits of farmed freshwater Labeo rohita in relation to body size as important information to calculate yield and/or support for machine/manual processing. For this purpose ninety specimens were collected for nine weight groups from 600 to 1100 g, each group with a 100 g increment. Specimens were collected from grow‐out culture ponds of...

article

High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes

F. Garcia-Herrero, M. J. Canet, J. Valls, P. K. Meher

IEEE Transactions on Very Large Scale Integration (VLSI) Systems > 2012 > 20 > 3 > 568 - 573

In this paper, a high-throughput interpolator architecture for soft-decision decoding of Reed–Solomon (RS) codes based on low-complexity chase (LCC) decoding is presented. We have formulated a modified form of the Nielson's interpolation algorithm, using some typical features of LCC decoding. The proposed algorithm works with a different scheduling, takes care of the limited growth of the polynomials,...

chapter

Efficient weighted modulo 2ⁿ+1 adders by partitioned parallel-prefix computation and enhanced circular carry generation

Tso-Bing Juang, P K Meher, Chin-Chieh Chiu

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test > 1 - 4

2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT 2011)

In this paper, we propose a low complexity design of weighted modulo 2ⁿ+1 adder, derived by decomposition of parallel-prefix computation into several blocks of smaller input bit-widths. Besides, we have proposed a novel enhanced circular carry generation (ECCG) unit to process the carry-bits produced by all the parallel-prefix computation units (of small input bit-widths) to obtain the final modulo...

chapter

High-performance logarithmic converters using novel two-region bit-level manipulation schemes

Tso-Bing Juang, P K Meher, Kai-Shiang Jan

Proceedings of 2011 International Symposium on VLSI Design, Automation and Test > 1 - 4

2011 International Symposium on VLSI Design, Automation and Test (VLSI-DAT 2011)

In this paper, we propose a high-performance logarithmic converter using novel two-region bit-level manipulation schemes. The proposed technique provides an area-time-efficient hardware implementation, since it avoids the need of a ROM by using simple arithmetic operations instead. Accuracy analysis shows that the proposed converter can achieve an error range and percent error range of only 0.0319...

article

Development of Laguerre Neural-Network-Based Intelligent Sensors for Wireless Sensor Networks

J C Patra, P K Meher, G Chakraborty

IEEE Transactions on Instrumentation and Measurement > 2011 > 60 > 3 > 725 - 734

The node of a wireless sensor network (WSN), which contains a sensor module with one or more physical sensors, may be exposed to widely varying environmental conditions, e.g., temperature, pressure, humidity, etc. Most of the sensor response characteristics are nonlinear, and in addition to that, other environmental parameters influence the sensor output nonlinearly. Therefore, to obtain accurate...

article

Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT

B K Mohanty, P K Meher

IEEE Transactions on Signal Processing > 2011 > 59 > 5 > 2072 - 2084

In this paper, we present a modular and pipeline architecture for lifting-based multilevel 2-D DWT, without using line-buffer and frame-buffer. Overall area-delay product is reduced in the proposed design by appropriate partitioning and scheduling of the computation of individual decomposition-levels. The processing for different levels is performed by a cascaded pipeline structure to maximize the...

article

High-Speed RS(255, 239) Decoder Based on LCC Decoding

F. García-Herrero, J. Valls, P. K. Meher

Circuits, Systems, and Signal Processing > 2011 > 30 > 6 > 1643-1669

Algebraic Soft-Decision Decoding (ASD) of Reed–Solomon (RS) codes provides higher coding gain over the conventional hard-decision decoding (HDD), but involves high computational complexity. Among the existing ASD methods, the Low Complexity Chase (LCC) decoding is the one with the lowest implementation cost. LCC decoding is based on generating 2^η test vectors, where η symbols are selected as the...

chapter

Memory-Based Computation of Inner-Product for Digital Signal Processing Applications

P K Meher

2010 International Symposium on Electronic System Design > 95 - 100

2010 International Symposium on Electronic System Design (ISED 2010)

In this paper, we present the optimization schemes for the implementation of inner-products using distributed arithmetic (DA) and look-up-table (LUT)-based multipliers. The optimized designs of both these approaches need the same number of LUTs and the same number of adders to produce the same throughput rate. But, the DA-based design needs adders of less width, while the LUT-multiplier based design...

chapter

Low-Cost Design of Serial-Parallel Multipliers Over GF(2^m) Using Hybrid Pass-Transistor Logic (PTL) and CMOS Logic

P K Meher, Shen-Fu Hsiao, Chia-Sheng Wen, Ming-Yu Tsai

2010 International Symposium on Electronic System Design > 131 - 134

2010 International Symposium on Electronic System Design (ISED 2010)

We have designed pass-transistor logic (PTL)-based D flip-flop and T flip-flop to be used in finite field multiplication. Since both CMOS and PTL have their respective advantages in area, speed, and power, we have compared two different designs (conventional implementation and improved implementation) of serial-parallel finite field multiplication using pure CMOS, pure PTL, and hybrid PTL/CMOS logic...

chapter

Area-efficient parallel-prefix Ling adders

Tso-Bing Juang, P K Meher, Chung-Chun Kuan

2010 IEEE Asia Pacific Conference on Circuits and Systems > 736 - 739

2010 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2010)

Efficient addition of binary numbers plays a very important role in the design of dedicated as well as general purpose processors for the implementation of arithmetic and logic units, branch decision, and floating-point operations, address generations, etc. Several methods have been reported in the literature for the fast and hardware-efficient realization of binary additions. Among these methods,...

article

Derivation and characterization of embryonic stem‐like cells of Indian major carp Catla catla

C. Dash, P. Routray, S. Tripathy, D. K. Verma, more

Journal of Fish Biology > 77 > 5 > 1096 - 1113

Embryonic stem (ES)‐like cells were derived from mid‐blastula stage embryos of a freshwater fish, catla Catla catla, under feeder‐free condition and designated as CCES cells. The conditioned media was optimized with 10% foetal bovine serum (FBS), fish embryo extract (FEE) having 100 µg ml⁻¹ protein concentration, 15 ng ml⁻¹ basic fibroblast growth factor (bFGF) and basic media containing Leibovitz‐15,...

chapter

LUT-based circuits for future wireless systems

P K Meher

2010 53rd IEEE International Midwest Symposium on Circuits and Systems > 696 - 699

2010 53rd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2010)

The future wireless systems have three mutually conflicting demands, e.g., high computational-bandwith, low-power consumption and reconfigurability. Such a set of demands will continue to be a challenge to the designers of computing circuits and systems for the next generation wireless communication. The lookup-table (LUT)-based arithmetic circuits have significant potential to satisfy these requirements...

chapter

DNA microarray analysis using Equalized Orthogonal Mapping

J C Patra, N V George, P K Meher

The 2010 International Joint Conference on Neural Networks (IJCNN) > 1 - 8

2010 International Joint Conference on Neural Networks (IJCNN 2010)

Gene expression data obtained from DNA microarray experiments consists of expression levels of thousands of genes of only a few samples. Thus, accurate analysis of these datasets for classification of cancer is a big challenge. In this paper, we apply a novel Equalized Orthogonal Map (EOM) as a dimension reduction technique to produce topologically correct map of DNA microarray data for visualization...

article

Parallel and Pipeline Architectures for High-Throughput Computation of Multilevel 3-D DWT

B K Mohanty, P K Meher

IEEE Transactions on Circuits and Systems for Video Technology > 2010 > 20 > 9 > 1200 - 1209

In this paper, we present a throughput-scalable parallel and pipeline architecture for high-throughput computation of multilevel 3-D discrete wavelet transform (3-D DWT). The computation of 3-D DWT for each level of decomposition is split into three distinct stages, and all the three stages are implemented in parallel by a processing unit consisting of an array of processing modules. The processing...

article

Algorithm for efficient interpolation of real-valued signals using discrete hartley transform

G. S. Maharana, P. K. Meher

Computers and Electrical Engineering > 1997 > 23 > 2 > 129-134

A scheme for interpolation of discrete-time signals using the discrete Hartley transform (DHT), is deduced from the existing DFT-based scheme. Besides, a DHT-based fast interpolation algorithm is suggested. A comparative study of arithmetic and time complexities involved in the interpolation using different FFT and FHT algorithms is also presented. It is observed that the computational complexities...

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