The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Sizing of analog circuits is one important step in the analog design flow. State-of-the art sizing tasks frequently require discrete parameters to consider manufacturing grids, multipliers, or technologies with exclusively discretely scalable design parameters. This paper presents a new SQP and Branch and Bound based approach to tackle this problem. Experimental results show the efficacy and effectiveness...
This paper proposes an efficient method to predict the lifetime yield of analog circuits considering the joint effects of manufacturing process variations and parameter lifetime degradations. The method uses the idea of worst-case distance, which is an indicator of circuit robustness concerning process variations. The worst-case distance in circuit lifetime is predicted based on a new, quadratic prediction...
As integrated circuit technology scales down continuously, transistor parameters will shift from their nominal values due to process-induced variations and time-dependent degradations. While the former issue contributes directly to the production yield of the fresh circuit, the reliability issue will cause an additional yield loss during the lifetime. Thus the prediction of the circuit's lifetime...
In this paper, a new method for routing is presented that computes routes as piecewise connected polygons. First, it creates routes based on a modified Lee approach that prefers 45-degree connections. Second, the resulting routes are developed to shortest piecewise linear segments of any angle between pins and around corners of blocked areas. The underlying algorithm for this second step can be interpreted...
This paper gives an overview of some recent advances in topological approaches to analog layout synthesis and in layout-aware analog sizing. The core issue in these approaches is the modeling of layout constraints for an efficient exploration process. This includes fast checking of constraint compliance, reducing the search space, and quickly relating topological encodings to placements. Sequence-pairs,...
For a speed-up of analog design cycles to keep up with the continuously decreasing time to market, iterative design refinement and redesigns are more than ever regarded as showstoppers. To deal with this issue, referred to as design and verification gap, the development of a continuous and consistent verification is mandatory. In digital design, formal verification methods are considered as a key...
Sizing of analog circuits requires the consideration of both continuous and discrete design parameters, e.g. due to predefined manufacturing grids. In this paper, a new method is presented to solve this task. It is based on an iterative optimization process with random-based searches on search regions that are determined by performance gradients. Experimental simulation results of operational amplifiers...
Many methods for analog circuit sizing are available as commercial, in-house and academic tools. They are based on continuous optimization, e.g., of transistor geometries, although the subsequent layout step requires values on a pre-defined grid. In addition, sizing of transistors for bipolar and RF circuits frequently necessitates the use of multiples of predefined values for the design parameters...
This paper presents sizing rules for basic building blocks in analog bipolar circuit design. Sizing rules efficiently capture design knowledge on the technology-specific level of transistor-pair groups. This reduces the effort for and improves the resulting quality of analog circuit synthesis. We present a hierarchical library of transistor-pair groups as basic building blocks for analog bipolar circuits...
This paper presents an optimization method for switched-capacitor σ-δ modulators. The SNR performance is maximized while considering the performance capability of the critical building block, i.e. the Op Amp. Performance space exploration is applied to find the feasible region of the building block's performance, which is represented by a Pareto-optimal front. Through worst-case analysis on design...
Until recently, analog sizing decided a-priori by weight assignment the trade-off between competing design objectives. Nowadays, architectural design requires the knowledge of all possible optimal trade-offs of a building block. Methods for Pareto optimization provide the set of all optimal trade-offs, the so-called Pareto front. The next generation of analog Pareto optimization tools has to additionally...
One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as high gain or low power consumption. In most cases one performance can only be optimized at cost of others, therefore a sizing must aim at an optimal trade-off between the important circuit performances. This paper presents a...
In this paper, a hierarchical optimization methodology for charge pump phase-locked loops (CPPLLs) is proposed. It has the following features: 1) A comprehensive and efficient behavioral modeling of the PLL enables fast simulations and includes the important PLL performances jitter, power and locking time, as well as stability constraints for the nonlinear locking process and the linear lock-in state;...
In this paper we present a method for the fast evaluation of circuit structures. It is part of a methodology for the structural synthesis of analog circuits which generates a large number of different circuit structures. Goal of the presented methods is to find circuit structures, which fit best the design goals. Based on implicit analog circuit specifications, as well as explicit performance specifications...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.