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Dependence of CDM discharge current on the tester geometry is studied by modifying its charge and ground plates. The result on a wide range of device size shows a strong dependence on the ground plate area. The need for a revised specification is discussed.
Comparison between single pulse and standard three pulse testing is presented for Charged Device Model (CDM). It is proposed that single pulse per pin testing should be sufficient for reliability. This method avoids issues due to the cumulative nature of multiple pulses and is a closer representation of real world.
Effect of device size on the peak CDM current is discussed. The current increases monotonically for small packages and then saturates for sizes larger than 1000 mm2. Size of the charge plate of the CDM tester contributed to this behavior. The current was not found to be constant across the package. Instead, it showed maximum value in the middle and minimum at the outer edge. An unexpected variation...
We report an unusual ESD failure when testing according to the recommended stress combination of IO to all other IO pins. In two independent product cases we observed devices failing for this test while the same devices pass when tested for all possible IO pin to IO pin combinations. These results strongly suggest a revision of this test methodology.
A previously undetected trailing pulse from HBM testers was found to create unexpected gate oxide failures on new technologies. This secondary pulse, which is EOS in nature, is caused by the discharge relay and the parasitics of the charge circuit. This paper investigates this critical phenomenon and establishes the tester improvements to safely suppress the trailing pulse effects.
In the present work, we have integrated TLP analysis into our troubleshooting efforts for product-level ESD protection designs. We have demonstrated the application of the TLP analysis to understand a unique HBM ESD failure and to arrive at the necessary corrective actions to optimize the product ESD design.
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