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A 56Gbps PAM-4 optical receiver front-end is presented. In order to reduce the input-referred current noise of the receiver front-end, the shunt feedback resistor Rf of the TIA is enlarged. And, the equalizer is inserted to boost the high-frequency gain and extend the bandwidth. The AGC amplifier using the proposed dB-linear VGAs is further to lower the noise. This PAM-4 optical receiver front-end...
A digital multiplying delay-locked loop (DMDLL) is presented to reduce the low-frequency phase noise and lower the power. The main divider is also turned off to reduce the power. The digitally-controlled oscillator uses the switched biasing technique to reduce the low-frequency phase noise. This DMDLL is fabricated in 40-nm CMOS technology and its active area is 0.0088 mm2. The output frequency of...
A 10–20 Gb/s clock and data recovery (CDR) circuit with frequency tracking is presented. Two digital phase interpolators (PIs) are used to track the frequency of input data. The loop bandwidth of the CDR circuit is adaptively adjusted. A mixed-mode PI is used to generate the recovered clock. This CDR circuit is fabricated in a 40nm CMOS process and its area is 0.33×1.0 mm2. Its power consumption is...
Phase-locked loops (PLLs) are widely used in various applications such as processors, consumer electronics, and wireline communication systems. When digital circuits and a PLL with a ring oscillator are integrated together, the power supply noise may degrade the jitter performance of the PLL. To lower the supply-noise sensitivity of a PLL, several approaches [1-5] have been proposed. A passive decoupling...
A digital bang-bang phase-locked loop (BBPLL) with bandwidth calibration is presented. The proposed bandwidth calibration circuit adjusts the proportional and integral gain of the digital loop filter to tolerate the process, voltage and temperature (PVT) variations. This BBPLL is fabricated in 40-nm CMOS technology. Its active area is 0.0049 mm2 and the power is 3.34 mW from a supply of 1.1 V. The...
This paper presents a digital bang-bang phase-locked loop that employs automatic loop gain control and loop latency reduction techniques to enhance the jitter performance. The chip is fabricated in a 40nm CMOS process. This bang-bang phase-locked loop achieves 290fsrms integrated jitter and reference spurs <-72.89dBc. It consumes 3.8mW from a 1.1V supply while operating at 3.96GHz. This translates...
A 0.3V 10-bit rail-to-rail successive approximation register (SAR) analog-to-digital converter (ADC) is realized in 0.18-μm CMOS process. While the supply is 0.3V, a double-boosted sampling switch and a supply-boosted time-domain comparator are proposed to decrease the on-resistance of the switches and improve the conversion time, respectively. To lower the power, differential dynamic switches are...
A small-area energy-efficient true random number generator (TRNG) is presented. This TRNG introduces a jitter signal generator to realize the noise pre-amplification, and utilizes a metastable latch to resolve the jitter edges. Moreover, to tolerate the process and environment variations, an offset calibration is employed to dynamically correct the bias of the probability of logic 0/1 in background...
A 2×25 Gb/s clock and data recovery circuit is fabricated in a 40-nm CMOS process. A background amplitude-locked loop is proposed to reduce the amplitude variation of a charge-steering-logic return-to-zero latch. The measured rms jitter is 2.26 ps and the peak-to-peak jitter is 15.56 ps for a 25 Gb/s PRBS of 27-1. It dissipates 8.8 mw per channel from 1.15 V supply.
A 5–20Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) using edge counting is fabricated in 40-nm CMOS technology. The power of this CTLE is adjusted according to the bit rates to improve the power efficiency. An edge counting technique with an asynchronous clock is presented to adaptively adjust the gain and power of this CTLE. All the measured bit error rates are less than 10...
A low-input-swing AC-DC voltage multiplier using Schottky diodes is presented. The equivalent model of the voltage multiplier is developed and analyzed. To enhance power conversion efficiency (PCE), a matching network is added. For a multiple-stage voltage multiplier, a limiting circuit is added for over-voltage protection. A single-stage/three-stage voltage multiplier with a limiting circuit is fabricated...
Silicon nanowire-based biosensors have been identified as a promising biosensing technology. However, it suffers from the interface signal process to be applied into applications. In this paper, we utilize a readout circuit to directly transfer the signal obtained from a Si nanowire based sensing device into digital format. Based on the experimental results, cTnI and NT-proBNP, the biomarkers for...
A 20Gb/s adaptive duobinary transceiver has been realized in 90-nm CMOS technology. An adaptive transmitter is realized without a feedback channel. For the channels with different lengths, the tap coefficient of the transmitter is digitally adjusted to compensate the channel loss. It achieves a data rate of 20-Gb/s with a BER less than 10−12 over 16cm-FR4 board. The transmitter and receiver consume...
An ultrasonic telemetry and a neural stimulator are presented. The wireless charging, data transmission and neural stimulation are demonstrated in this work. A frequency-shift keying with pulse-width modulation is adopted for wireless charging and data transmission. The stimulator provides an output current of 0μA~900μA. The frequency of the current pulse is from 60Hz to 320Hz. This ultrasonic telemetry...
A low-phase-noise phase-locked loop (PLL) is widely used in clock generation, frequency synthesis, and data conversion. In [1,2], a PLL using a sub-sampling phase detector (SSPD) achieves not only low phase noise, but also low power. In [3–5], a low-phase-noise sub-harmonically injection-locked PLL (SIPLL) is presented. The injection timing of a SIPLL is sensitive to the process, voltage, and temperature...
A fast-locking phase-locked loop (PLL) using a CP control and a gated voltage-controlled oscillator is presented. This PLL is fabricated in a 90nm CMOS technology. The measured locking time is 3.78us from 640MHz to 800MHz. This PLL consumes 3.8mW for a supply of 1.2V and the active area is 0.0135mm2.
A low-phase-noise integer-N phase-locked loop (PLL) is attractive in many applications, such as clock generation and analog-to-digital conversion. The sub-harmonically injection-locked technique [1–3], sub-sampling technique [4], and the multiplying delay-locked loop (MDLL) [5–8] can significantly improve the phase noise of an integer-N PLL. In the sub-harmonically injection-locked technique, to inject...
Delay-locked loops (DLLs) are widely adopted for clock generation and synchronization in high performance digital systems. The design of analog DLLs has become a challenge due to the trends associated with CMOS scaling, namely, high leakage current, low supply voltage, etc. Consequently, many designers have shifted their focus to digitally-assisted or all-digitally implemented DLLs, which are easier...
A leakage-current-recycling technique is presented for phase-locked loops (PLLs) in nanoscale CMOS technology. The leakage current of the PMOS capacitor in a PLL is recycled to supply the power for a voltage-controlled oscillator, a divider and a dual-mode phase-frequency detector. This PLL is fabricated in a 65nm CMOS technology. The measured peak-to-peak jitter and rms jitter of this PLL at 640MHz...
Two 3.6mW D-band divide-by-3 injection-locked frequency dividers (ILFDs) are realized in a 65nm CMOS process. The power consumption is 3.6mW for a supply of 1.2V. By using a second-harmonic enhancement technique, a divide-by-3 ILFD achieves a locking range of 130.01∼132.4GHz. To the authors' best knowledge, this is the first divide-by-3 CMOS ILFD to work at D band.
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