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We propose a microphone array network that realizes ubiquitous sound acquisition. Nodes with 16 microphones are connected to form a large sound acquisition system that carries out voice activity detection (VAD), sound source localization and sound source separation. The three operations are distributed among nodes using network. Because the VAD is implemented to manage power consumption, the system...
We present a small-area 10T SRAM cell without half selection problem. As well, the proposed 10T cell achieves a faster access time and low voltage operation. The cell area is reduced by 25%, and the cell current is increased by 21%, compared with the prior 10T cell. The minimum operating voltage is lowered by the column line assist (CLA) scheme that suppresses write margin degradation. By measurement,...
In this paper, 40 Gb/s SFI-5-compliant TX and RX chips in 65 nm CMOS technology consume 2.8 W each. This low power dissipation allows for a small and low-cost plastic BGA package. The TX has a full-rate clock architecture that is based on a 40 GHz VCO, a 40 Gb/s retiming D-FF, and 40 GHz clock-distribution circuits that lead to a low jitter of 0.57 psrms and 3.1 pspp at 40 Gb/s. A 40/20 GHz clock-timing-adjustment...
We propose a low-power two-port SRAM for real-time video processing that exploits statistical similarity in images. To minimize the discharge power on a read bitline, a majority-logic circuit decides if input data should be inverted in a write cycle, so that ldquo1rdquos are in the majority. In addition, for further power reduction, write-in data are reordered into digit groups from the most significant...
This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM, in a 45-nm process and later with large threshold-voltage variation. The proposed voltage-control scheme that improves a write margin and read current, and the write-back scheme that stabilizes unselected cells are applied to the 8T SRAM. We verified that the low-voltage operation...
We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus, power is not consumed by precharging, but is...
This paper proposes a voltage-control scheme for an SRAM that makes a minimum operation voltage down to 0.3 V even on a future memory-rich SoC. A self-aligned timing control guarantees stable operation in a wide range of Vdd under DVS environment. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that 30% power reduction is achieved at 100 MHz. The area overhead is only 5.6%
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