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In this paper, 40 Gb/s SFI-5-compliant TX and RX chips in 65 nm CMOS technology consume 2.8 W each. This low power dissipation allows for a small and low-cost plastic BGA package. The TX has a full-rate clock architecture that is based on a 40 GHz VCO, a 40 Gb/s retiming D-FF, and 40 GHz clock-distribution circuits that lead to a low jitter of 0.57 psrms and 3.1 pspp at 40 Gb/s. A 40/20 GHz clock-timing-adjustment...
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