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Image edge detection plays an important role in applications such as handwriting and face recognition, corner and obstacle detection. This paper presents a web server-client implementation for remote image processing applications. The web server is implemented using the Microblaze soft-processor core in FPGA. The edge detection kernels are mapped on QUKU, which is a coarse grained dynamically reconfigurable...
We demonstrate a hybrid reconfigurable cluster-on-chip architecture with a cross-platform Message Passing Interface (MPI), a cross-platform parallel image processing library and a sample application. We describe the system, network architecture, MPI library and the parallel image processing library implementations. We validate the performance, scalability and suitability of MPI as a software interface...
This paper describes the integration and performance of a multi-stream cipher core with a uClinux Microblaze based reconfigurable system-on- chip that uses the Open Crypto framework. This allows applications to access the multi stream cipher core via kernel space calls.
A technique is presented which allows an FPGA-based reconfigurable system-on-chip to automatically and dynamically load hardware peripheral controllers and software device drivers depending on the system's automated identification of peripheral boards which are connected to the FPGA. The technique loads peripheral detection modules into peripheral controller slots at system startup, and after these...
DSP applications can be suitably represented using process network models. This paper uses a modification of Kahn process network to solve the problem of finding an optimum architectural template for coarse grain array on per application basis. By applying the model at architectural level in QUKU, better hardware efficiency is achieved for a wide domain of applications. A few widely used DSP algorithms...
In this paper, the authors present a reconfigurable cluster-on-chip architecture and supporting parallel programming software library based on the well-known message passing interface (MPI) standard. The intent is to allow designers to program multi-core reconfigurable systems on chip using the same or similar methodologies that yielded tremendous productivity improvements in the workstation and HPC...
The post integration performance of cipher cores to a reconfigurable system-on-chip is a relatively unexplored area. There is also little work done on a stream aware cipher core. This paper presents an architecture that allows a cipher core to operate on multiple cipher streams without context switching. The integration of this architecture using fast simplex links to the microblaze soft-processor...
FPGAs have been used for prototyping of ASICs, for low-volume ASIC replacement and for systems requiring in-field hardware upgrades. However, the potential to use dynamic reconfiguration to adapt FPGA operation to changing application requirements has been hampered by slow reconfiguration times, and poor CAD tool support. In this paper, a new architecture, QUKU (pronounced cuckoo), is described which...
Optical character recognition (OCR) systems improve human-machine interaction and are widely used in many areas. The recognition of cursive scripts is a difficult task as their segmentation suffers from serious problems. This paper proposes an Arabic OCR system, which uses a recognition-based segmentation technique to overcome the classical segmentation problems. A newly developed Arabic word segmentation...
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