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In this presentation we shortly discuss the evolution of Microelectronics into Nanoelectronics, according to the predictions of Moore's law, and some of the issues related with this evolution. Next, we address the requirements of device modeling related with an extreme device miniaturization, such as the band splitting into multiple subbands and quasi-ballistic transport. Physical models are summarized...
Design of complementary n- and p-type heterojunction tunnel field-effect transistors (TFETs) realized with the same InAs/Al0.05Ga0.95Sb material pair is carried out in this work using 3D, full-quantum simulations. Several design parameters are optimized, leading to a TFET pair with similar dimensions and feasible aspect ratios, which exhibit average subthreshold slopes around 30 mV/dec and relatively...
Effect of transverse quantization on the broken vs. staggered band lineup of InAs/Al xGa1−xSb TFETs is investigated, showing that cross-sections up to 1 0nm lead to staggered configurations for any value of the Al mole fraction x. Device performance is optimized as a function of cross-sectional size, Al content and possible source/channel underlap, while ensuring low standby power (LSTP) or low operating...
FinFET is a promising architecture for low-voltage/low-power applications at and beyond the 32 nm technology generation. VDD scalability of LSTP- and LOP-32 nm compatible FinFET SRAMs is investigated in the presence of fin line-edge roughness (LER). Several design options are compared, including transistor sizing, mobility changes as a result of crystal orientation, fin patterning and gate stack,...
As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. At sub-45 nm nodes, in which FinFET is a viable device architecture, line-edge roughness (LER) in current Si-based technologies forms a significant fraction of the line CD. In such cases, analyzing the impact of LER on FinFET performance is vital for meeting various device specifications. The impact...
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