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Continuous scaling down NAND FLASH toward below 2Xnm node generation will result in serious Floating Gate (FG) poly depletion due to dopant loss and significantly degrade the cell reliability performance. FG implantation (IMP) before inter-poly-dielectric (IPD) deposition was proposed in this study, but it suffered FG damage and resulted in control gate (CG) void issue. We have successfully minimized...
We have developed a new Self-aligned poly (SAP) process to improve the tunnel oxide integrity by optimizing the shallow trench isolation (STI) corner rounding profile and reducing the local oxide thinning effect. It is found that double in-situ steam generation (ISSG) liner oxides can effectively improve the STI corner rounding. As for the local oxide thinning effect, the composite pad dielectrics...
For Solid-State Drive (SSD) applications cycling endurance of NAND flash is a critical challenge. In this work the endurance reliability of BE-SONOS NAND is thoroughly examined. Using dual CV/IV tests the impact of interface state (Dit) generation/annealing and real charge trapping (Q) on the endurance degradation has been clearly identified. For BE-SONOS with pure thermal oxide O1, the endurance...
Bandgap-tunable SiON (oxynitride) tunnel barrier is developed to optimize the performance and reliability of BE-SONOS NAND Flash devices. The HTO O2 layer of the ONO tunnel barrier is replaced by SiON thin films with various refractive index (n) and thickness. We found that with n ≤ 1.72, SiON can provide excellent data retention comparable to conventional BE-SONOS. On the other hand, the erase speed...
The reliability properties of BE-SONOS (Lue et al., 2005) are extensively studied. BE-SONOS employs a multi-layer O1/N1/O2/N2/O3 stack, where O1/N1/O2 serves as a bandgap engineered tunneling barrier that provides an efficient hole tunneling erase but eliminates the direct tunneling leakage. BE-SONOS can overcome the fundamental limitation of the conventional SONOS, for which fast erase speed and...
A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) flash memory. A TFT device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai et al., 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.2/0.09 mum) with excellent performance and reliability...
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