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This paper describes design techniques of enabling energy-efficient 3-tap decision feedback equalizer (DFE) to operate adaptively at 40Gb/s in 65nm CMOS technology. First, we propose a closed-loop architecture utilizing three techniques to achieve the 1st tap stage design, namely a merged latch and summer, reduced latch gain, and a dynamic latch design. Then, we suggest to merge the feedback MUX with...
This paper presents a single loop 3rd order 5-bit audio ΣΔ modulator with feed forward path. Feed forward technology relaxes the amplifier design requirement by reducing output swing of the integrators. Chopper stabilization technology is employed to mitigate the flicker noise introduced by 1st integrator. A kind of asynchronous successive approximation (SAR) quantizer without extra fast clock replaces...
This paper presents a discrete time ΔΣ modulator operating under 1V power supply. To achieve high precision under low voltage while preserve low power consumption, techniques from systematic level to circuits' level are used. On the systematic level, modulator with 4-bit quantizer is employed. The advantage is its excellent stability performance which extends input signal range near to the reference...
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