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An effective optimization approach for the electromigration (EM) reliability in power grid (PG) has been presented in this paper. With core technology development and the key feature size of integrated circuits decreasing, it is more serious for the EM-induced failure occurrence in the entire PG. However, previous PG studies focus on supply noise optimization and neglect the EM influence in lines,...
Transient analysis is the most practical and effective approach for power grid validation, but which is very chal-lengeable for large scale VLSI chips because it is really time consuming and requires large memory resources. In this paper we proposed a parallel transient simulation approach for efficient power grid analysis. Firstly we adopt symmetric formulation for NA equation of RLC power grid to...
In this paper, we propose a fast placer for FPGA placement on a new commercial hierarchical FPGA device. The novelty of this research lies in the application of a multilevel V-shape optimization flow including an architecture related cluster process and a constructive placement. The new placer can handle large-scale FPGA placement problem quickly. Experimental results show that the proposed placer...
In this paper, we present a top-down global placement algorithm considering wire density uniformity for CMP variation control. The proposed algorithm is based on top-down recursive bisection framework. Wire weight balancing constraint is employed into bisection to consider wire density uniformity. A multilevel hypergraph partitioning satisfying balancing constraints on not only cell area but also...
In this paper, we present a multilevel hierarchical FPGA (MFPGA) architecture model and propose a cluster-based placement algorithm for this model. The algorithm has a multi-scale optimized V-shape flow including constructive bottom-up clustering process and top-down placement process. Experimental results indicate that our algorithm improves total wire-length and logic utilization by more than 15%...
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