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In this paper, memory devices integrating a double layer of silicon nanocrystals (Si-ncs) as a trapping medium and a HfAlO-based control dielectrics are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared with the single Si-nc layer devices, without introducing anomalies on the charging dynamics. Then, we also evaluate the potential use...
In this paper it is shown that HfO2 and HfZrO oxides suffer from large VT instabilities, up to 230mV, when the device width (W) is scaled down to 80nm. It is explained by undesirable lateral oxygen diffusion through the spacers, which mainly modifies the metal workfunction in narrow transistors. HfSiO(N) oxides exhibit a much better immunity to this effect, attributed to a different crystallinity...
In this work we present the integration of Band Engineered TANOS-like memories using HfSiON in the tunnel stack to boost the programming efficiency and improve cycling. An accurate correlation analysis between the gate-stack material physical properties and the memory performances is presented. In particular, the importance of the nitridation step of HfSiON on the memory retention characteristics...
Al incorporation in the High-κ/metal gate stack is studied for pMOS transistors application. Al is here incorporated before or after high-k deposition, or during the metal deposition. Using bevelled oxides and Internal photoemission (IPE), we discriminate and quantify the three key mechanisms shifting the effective metal workfunction WFMeff: (1) a dipole (up to ~1 eV!) build up at the SiO2/High-κ...
Silicon nanocrystal (Si-nc) trapping layers offer several advantages on standard poly-Si floating gates, as improved data retention after endurance in particular at high temperatures, robustness toward oxide defects, two-bits per cell storage and full compatibility toward CMOS process. It has also been shown that coupling the Si-nc concept with high-k control dielectrics, by improving the gate coupling...
In this work, memory devices integrating a double layer of silicon nanocrystals as trapping medium and a high-k HfAlO-based control dielectric are presented. We will show that the use of two stacked Si-nc layers significantly improves the memory window compared to the single Si-nc layer devices, without introducing dispersions on the charging dynamics. Then, we also evaluate the potentiality of hybrid...
The goal of this work is to give a clear physical comprehension of the charge loss mechanisms of SANOS (Si/Al2O3/Si3N4/SiO2/Si) memories. Retention at room and high temperature is investigated on different samples through experiments and theoretical modeling. We argue that at room temperature, the charge loss essentially results from the tunneling of the electrons trapped at the nitride interface,...
In this work, we present an experimental and theoretical study of nitride trap devices with a HTO/Al2O3 bi-layer blocking oxide. Such SAONOS (Silicon/Alumina/HTO/Nitride/Oxide/Silicon) devices are compared with standard SONOS (Silicon/HTO/Nitride/Oxide/Silicon) and SANOS (Silicon/Alumina/Nitride/Oxide/Silicon) memories. The role of the different layers (blocking oxide and control gate) is deeply analyzed,...
In this paper, different Hf-based oxides (HfO2, HfSiO under several annealing conditions, HfSiON, HfAlO with various compositions) are simultaneously considered as storage layers of charge-trap memories. Based on material characterization analyses, electrical data of memory cells, physical modeling of charge-trap devices, we show that a strict relationship exists between the crystal structure of the...
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