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Instruction scheduling is a crucial issue for cutting edge VLSI processors that exploit parallelism to solve the tradeoff between clock speed and power dissipation. A double scheme for multiple pipelines merges their scalar units into a multifunctional unit (MFU) and makes the MFU wave-pipeline. Parallelizing a resultant pipeline achieves instruction scheduling free due to multifunctionality. Applied...
Power conscious strong security and multimedia reality are demanded for the construction of emerging ubiquitous environment. Since multimedia computing requires high performance, high precision, and real time responsibility, the hardware approach or VLSI implementation of sophisticated strategies is one of the most promising solutions to satisfy those features. In developing cutting edge VLSI processors,...
One of crucial points for ubiquitous network is to keep the temporary security without relying on permanent network infrastructure. Considering a practical solution of ubiquitous security is a safety aware, high-performed single chip processor, we have exploited a multimedia stream cipher engine and its VLSI chip implementation. In order to keep security, usability, speed, and power consciousness,...
As semiconductor technologies are aggressively advanced, the problem of parameter variations is emerging. Process variations in transistors affect circuit delay, resulting in serious yield loss. Considering the situations, variationaware designs for yield enhancement interest researchers. This paper investigates to exploit the statistical features in circuit delay and to cascade dependent instructions...
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay has variability. Increasing the supply voltage to reduce the delay should not be a solution, since it increases power consumption, which is another serious problem in microprocessor designs. This paper proposes to combine recently-proposed...
VLSI is a significant area of ever growing ICT. In the development of cutting edge VLSI processors, parallelism is one of the most important global standard strategies to achieve power conscious high performance. These features are more critical for ubiquitous systems with a great demand. In order to fully utilize hardware parallelism, software parallelism like TLP and ILP is also inevitable. Considering...
This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a...
Intelligent mobile information devices require low-power and high-performance processors. In order to reduce energy consumption with maintaining computing performance, we proposed to utilize information regarding instruction criticality. Every functional unit in our processor has different latency and energy consumption. Only critical instructions are executed in power-hungry units, and the total...
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay also has variations. Recently, variable latency adders and long latency adders are proposed to manage the variation problem. Unfortunately, replacing a variation-affected adder with the long latency one has severe impact on processor performance...
As deep submicron technologies are advanced, we face new challenges, such as power consumption and soft errors. A naive technique, which utilizes emerging multicore processors and relies upon thread-level redundancy to detect soft errors, is power hungry. It consumes at least two times larger power than the conventional single-threaded processor does. This paper investigates a trade-off between dependability...
Instruction window is a key component which extracts instruction level parallelism (ILP) in modern out-of-order microprocessors. In order to exploit ILP for improving processor performance, instruction window size should be increased. However, it is difficult to increase the size, since instruction window is implemented by CAM whose power and delay are much large. This paper introduces a low power...
The key to protect huge amount of multimedia data in ubiquitous networks is to introduce safety aware high-performed single VLSI processor systems embedded with cipher process. Thus, we exploited the architecture of a hardware cryptography-embedded multimedia mobile processor named HCgorilla by sophisticatedly unifying up-to-date processor techniques. Although it was provided with carefully selected...
A real-time on-die noise sensor continuously detects up to 100 noise events per second without disturbing processor operations, using a 400kb/s serial interface. The noise sensor uses histogram counters and variable detection windows. The sensor measures periodic and single-events in real time. The noise sensor is implemented in a 90nm CMOS testchip.
Ever growing ubiquitous environment makes overall demands for security, speed, and power consciousness in processing huge amount of multimedia data. A practical solution to meet these demands is a safety aware, high-performed, and sophisticated single chip processor. According to this scheme, we have exploited a hardware cryptography-embedded multimedia mobile system composed of a dedicated processor...
With advance in silicon technology and system integrating technology, utmost care for RC-delay must be taken in high performance LSI design. This paper describes the new design method applied to the Vector Unit (VU) implemented in the recently announced high-performance 3D-graphics engine, 'Emotion Engine'. The key features of the design method are the following: careful functional design of the VU...
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