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A technique for controlling rush current and wake-up time of thick-gate-oxide power switches is described. Suppressing the variation of rush current on PVT allows shorter wake-up times, which can reduce leakage currents in a mobile processor. Wake-up takes 1.92 μs and leakage current is reduced by 96.9% in an application CPU domain. Probing the rush current indicated accurate control by the technique.
A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method can achieve very low leakage current in the partial active mode of a single chip mobile processor. The single chip mobile processor embedded three CPU's that is baseband processor, application processor, and multimedia processor...
Hierarchical power distribution using a power tree is developed. It supports fine-grained power gating with dozens of power domains like fine-grained clock gating and effectively reduces leakage currents for 1-million-gate power domains to 1/4000 in multi-CPU processors with minimal area overhead. This paper demonstrates the integration of 20 power domains in a 90nm single-chip 3G cellular phone processor
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