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A liquid crystal (LC) cell made of silicon (Si) electrodes was fabricated to achieve self-routing of optical signals. As optical pulses (1.06 μm wavelength) passed through the cell, they excited free carriers in the Si electrode, which triggered the voltage application to the LC layer. Consequently, the polarization direction of the succeeding pulses became perpendicular to that of the preceding pulses,...
We have investigated the effects of irradiation on space solar cell degradation characteristic. We examined the effects of beam conditions such as fluence rate and beam expansion method. For the fluence rate experiment, in the case of proton irradiations, the degradation did not depend on fluence rate. Meanwhile, in the case of electron irradiation, Si cell results showed degradation dependent on...
According to ITRS2009, the detection of 18nm particles is required for 2010, but the latest laser scattering wafer inspection system is not capable of detecting particles smaller than 28 nm. Therefore, it is necessary to establish the method of detecting smaller particles. We developed a method to detect particles that are below the detection limit of the particle detection system by depositing SiO...
We comparatively investigated the impact of layout and trench on four types of field oxide Pch MOSTs in a thick film SOI technology with due consideration to isolation trench. High blocking capability (~20 V per um of drift length) for both off- and on- state breakdown voltage close to 300 V, along with reasonable high temperature reverse bias ruggedness, has been experimentally realized with minimum...
An optical gate was fabricated with silicon, liquid crystal, and a polarizer. Photons excited free carriers in silicon, which triggered voltage application to the cell. Consequently, optical signals opened or closed their path by themselves.
We demonstrated 40nm gate length "gate overlapped raised extension structure: GORES MOSFET" without halo implantation and prove that the ultra shallow junction (USJ) could coexist with the reducing parasitic resistance in GORES MOSFET. It is the new concept planar transistor with the gate overlapping the in-situ doped epitaxial extension to break through the trade off relation between reducing...
A raised source/drain extension (RSDE) pFET on (110) Si wafer is demonstrated for the first time with in-situ doped selective epitaxy technology. Roll-off has been effectively improved, resulting from the elimination of ion channeling in (110) Si. Due to the hole mobility enhancement and parasitic resistance reduction, ion of 389muA/mum (Vd= -1.0 V) has been achieved at Lmin around 30nm extracted...
We have presented a design method of RF power Si-MOSFETs for low voltage and high power-added efficiency operation. It has been demonstrated that 0.2 /spl mu/m gate length Co-salicided Si MOSFETs can achieve high power-added efficiency of more than 50% at 2 GHz RF operation with sufficient breakdown voltage (V/sub dss/S) by choosing optimum gate oxide thickness and N/sup -/ extension impurity concentration...
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