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An 8 Tb/s 1 pJ/b 0.8 mm2/Tb/s inductive-coupling interface between 65 nm CMOS GPU and 0.1 ??m DRAM is developed. BER <10-16 operation is examined in 1024-bit parallel links. Compared to the latest wired 40 nm DRAM interface, the bandwidth is increased 32??, and the energy consumption and layout area are reduced by 8?? and 22??, respectively.
An inductive-coupling programmable bus for NAND flash memory access in solid state drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuit-layout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 ??m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips,...
The impacts of interfacial layer (IFL) thickness and crystallinity of HfO2/IFL bi-layer on electrical properties were clarified using synchrotron radiation photoemission spectroscopy (SRPES) and electrical measurements of nFETs (HfSix/HfO2) and pFETs (Ru/HfO2) including BTI. It was found that crystallization of HfO2 causes significant degradation in electron mobility and PBTI, whereas the impacts...
CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6...
We have developed a dual metal gate CMOS technology with HfSix for nMOS and Ru for pMOS on HfO2 gate dielectric. These gate stacks show high mobility (100% of universal mobility for electron, 80% for hole at high fields) down to Tinv of 1.7 nm and symmetrical low Vt equivalent to poly-Si/SiO2. As a result, high drive currents of 780 muA/mum and 265 muA/mum at Ioff = 1 nA/mum are achieved for Vdd...
High performance CMOSFET technology for 45nm generation is demonstrated. The key device strategies for junction scaling, gate stack scaling and stress-induced mobility enhancement are discussed. Reversed-order junction formation improves short channel effect (SCE) drastically. Novel SiON with improved poly-Si gate depletion improves the drive current by 8%. The systematic study on the process-induced...
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