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Three dimensional IC (3D IC) has lots of through-Si vias (TSVs) and metal microbumps for electrical connection between stacked IC chips, and also has organic adhesives to enhance the mechanical strength of 3D IC. However, the coefficient of thermal expansion (CTE) mismatch between microbumps and organic adhesives generate the local bending stress in thinned IC chips. Therefore, Keep-Out-Zone (KOZ)...
A novel approach to suppress the conventional Cu-TSV induced thermo-mechanical stress in 3D-LSI chip is proposed, fabricated and tested. In this approach, a thermal-chemical-vapor-deposition grown organic poly-imide based polymer is conformally deposited along the side wall of the TSV. As-grown polymer was tested for its physical properties and mechanical properties, and was also evaluated for their...
Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of the super-chip are described. In addition, the reliability challenges such as the mechanical stress/strain and Cu contamination are discussed. Cu TSVs with the diameter of 20-μm induced the maximum compressive stress of ∼1 GPa at the Si substrate adjacent to them after annealed at 300°C. Mechanical strain/stress...
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