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Classically, quasi-delay-insensitive asynchronous circuits based on weak-conditioned half-buffer employ the return-to-zero, 4-phase handshake protocol. This work scrutinizes the alternative return-to-one protocol and analyzes the effects of using it in practical circuits. A pipelined shift and add multiplier serves as case study. Return-to-one and return-to-zero versions of the circuit provide ground...
This work presents ASTRAN, a tool for automatic layout generation of cell libraries, and the use of this tool in the production of a cell library for asynchronous logic components called ASCEnD. In this context, ASTRAN is able to achieve orders of magnitude savings in cell generation time if compared to manual design. ASTRAN supports technologies down to 65nm and simultaneous two-dimensional cell...
Interest in asynchronous circuits has increased in the VLSI research community due the growing limitations faced during the design of synchronous circuits, which often result in over constrained design and operation. For designing asynchronous circuits quasi-delay-insensitive approaches are often preferable due to their simple timing analysis and closure. Null Convention Logic (NCL) is a style that...
The downscaling of silicon technology and the possibility of building MPSoCs, make intrachip communication a mainstream research topic. NoCs are an elegant solution to provide communication scalability and modularity. NoCs are already common in MPSoC design. Moreover, new technology challenges point to a growth in the use of non-synchronous NoCs. However, the design of asynchronous infrastructures...
Asynchronous paradigms are a way to deal with hard problems in newer technologies. Among the templates for ensuring efficient asynchronous design, Null Convention Logic (NCL) appears as a fast and relatively low area and power option, enabling semi-custom design. This work proposes a new asynchronous logic template, NCL+, which is a modification of NCL to support the return-to-one protocol. A basic...
Silicon technologies advances brought the possibility of integrating billions of transistors in a die. However, as transistors get smaller, some of the aspects that were negligible in previous technologies emerge as difficulties for the design in current and future technology nodes. In this context, fully synchronous circuits are harder to be built, as timing closure constraints become difficult to...
Asynchronous design techniques are gaining attention in the scientific community for their ability to cope with current technologies' problems that the synchronous paradigm may fail to cope with. In fact, fully synchronous SoCs may soon become unfeasible to build. Among multiple asynchronous design styles, the quasi delay insensitive (QDI) stands out for its robustness to delay variations. When coupled...
This demonstration presents the use of the Library Characterization Environment (LiChEn) for characterizing asynchronous standard cells. The tool was employed for the electrical characterization of a library with over five hundred asynchronous standard cells. In this work, a case study of a fundamental asynchronous component, the C-Element, will be presented to validate the use of the tool. LiChEn...
The scaling of microelectronic technologies brings new challenges to the design of complex SoCs. For example, fully synchronous SoCs may soon become unfeasible to build. Asynchronous design techniques increasingly mingle within SoC design procedures to achieve functional and efficient systems, where synchronous modules are independently designed and verified. This is followed by module integration...
This work presents the architecture and ASIC implementation of Hermes-AA, a flexible fully asynchronous network on chip router employing an adaptive routing algorithm. Hermes-AA enables communication between router and synchronous processing elements. The ASIC implementation of the router employed standard CAD tools and a specifically developed library of standard cell components. Area and timing...
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