The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The 3D extension of the High Efficiency Video Coding (HEVC) standard achieves large compression rates thanks to the addition of several tools to encode multiview and depth information on top of those available in HEVC. The use of such tools incur in a very large computational demand, which can be a serious problem in power and computationally-constrained devices and applications. However, not all...
This paper presents a low-power and high-throughput hardware design for the 3D-HEVC (Three Dimensional High Efficiency Video Coding) Depth Intra Skip coding tool. A strategy to reduce the computational effort was employed based on an analysis using the 3D-HEVC reference software. The proposed strategy consists of replacing the SVDC (Synthesized View Distortion Change) for the SAD (Sum of Absolute...
This paper presents a novel early Skip/DIS mode decision for 3D-HEVC depth encoding which aims at reducing the complexity effort of this process. The proposed solution is based on an adaptive threshold model, which takes into consideration the occurrence rate of both Skip and DIS modes. Occurrence analysis showed that the lower is the Skip and DIS Rate-Distortion cost, the higher is the probability...
3D-HEVC achieves significant compression efficiency thanks to the addition of several tools and features for multiview and 3D video content on top of those already available in HEVC. However, such gains come at the cost of large increases in the encoding computational complexity, which is a problem for computationally and battery-constrained devices. As the use of each tool or feature yields different...
This paper presented a hardware design of an 4-points IDCT inverse transform module defined in the newest video coding standard, the HEVC. This work proposes a simpler way to calculate the HEVC 4-points IDCT. This approach focuses in the occurrence of special cases where the result can be calculated without the full IDCT processing. These simplifications reduced about 87.5% the number of 1-D IDCT...
This work presents a hardware design for the Sample Adaptive Offset filter, which is an innovation brought by the new video coding standard HEVC. The architectures focus on the encoder side and include both classification methods used in SAO, the Band Offset and Edge Offset, and also the statistical calculations for the offset generation. The proposed architectures feature two sample buffers, classification...
This paper is focused on the inverse transforms defined in the HEVC (High Efficiency Video Coding) standard. The HEVC standard allows the use of four transform sizes, including novel transforms applied over bigger block sizes (16×16 and 32×32). The hardware architecture presented in this paper was planned to reach real-time processing (at 30 frames per second) for ultra-higher solution videos, exploiting...
This paper is focused on the Adaptive Loop Filter (ALF) which is responsible to reduce the distortion between an original image and the encoded image during the video coding process by fixing artifacts from previous stages. It was proposed a novel hardware design for the ALF core which is capable to process all ALF sizes (5×5, 7×7 and 9×9), saving hardware resources consumption through reuse. The...
This work presents a cost function optimization for the internal decision of the HEVC Sample Adaptive Offset (SAO) filter. The optimization approach is focused on an efficient hardware design implementation, and explores two critical points. The first one focus in the use of fixed-point data instead of float-point data, and the second focus on reduce the number of full multipliers and divisors. The...
This paper is focused in the inverse transforms defined in the video coding standard HEVC — High Efficiency Video Coding. The transforms stage is one of the innovations proposed by HEVC since it allows the use of the biggest number of transforms sizes (four) and also the biggest transform sizes (till 32×32) when compared with previous standards. The inverse DCT is performed by the video encoder and...
This paper presents the hardware design of a 16-points 1-D DCT used in the emerging video coding standard HEVC — High Efficiency Video Coding. The 1-D DCT is used by the 16×16 2-D DCT of the HEVC standard. The transforms stage is one of the innovations proposed by HEVC, not only because of the variable size (from 4×4 to 32×32) but also because higher dimension transforms other than the traditional...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.