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Reducing the configuration time of portions of an FPGA at run time is crucial in contemporary FPGA-based accelerators. In this work, we propose a method to increase the throughput for FPGA dynamic partial reconfiguration by using standard IP blocks. The throughput is increased by over-clocking the configuration bitstream circuitry beyond the limits stated in the specifications of these standard blocks...
Electric Encoders (EEs) are extensively used for position measurement in precise motion control. They are characterized by high resolution and simple circuit interface. Some EEs gauge the angle value exploiting a combination of coarse and fine measures. In both cases the outputs are the sine and cosine of angle. In this context the most delicate operation regards the measurement of initial angle,...
In this work, we apply hardware acceleration to embedded systems running audio applications. We present a new framework, Dynamically-Loaded Hardware Libraries or HLL, to dynamically load hardware libraries on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the...
Many cryptography algorithm contain a lots of data bit manipulation operations. Unfortunately, the Instruction Set Architecure (ISA) of general purpose microprocessors is usually word oriented. Consequently the execution of this kind of algorithms is not optimized and the computation of data represented by single bits or sub-words can require several clock cycles. Reconfigurable hardware accelerators...
Many software functions are not efficiently executed by standard microprocessors. This happens when the operation granularity and data wordlength are different with respect to those of the microprocessor's architecture. Important improvements in speed and power can be obtained by integrating hardware accelerators in standard microprocessor architectures. This work, based on [1], shows that the integration...
Nowadays programmable devices (microprocessors and DSPs) are based on complex architectures optimized for obtaining maximum speed performances that degrades when the implemented application is mostly based on operations on single bit or subset of bits. This kind of data processing and bit manipulation operations can be accelerated by using a Reconfigurable Functional Unit (RFU). In this paper the...
This paper describes the FPGA implementation of a low area and high Spurious Free Dynamic Range (SFDR) Direct Digital Frequency Synthesizer (DDFS). The proposed architecture derives from the one proposed in [1] and fits perfectly in modern FPGA having DSP Blocks and/or embedded multipliers. The DDFS model in [1] was modified in order to reduce further the ROM size by a factor of 2 without worsen the...
The execution of operations on data shorter than the native wordlenght usually decreases the performance of standard microprocessors. In order to overcome this issue, various methods, based on reconfigurable structures, have been presented in literature. These structures are normally realized as an array of elementary reconfigurable cells. A common solution for the realization of elementary reconfigurable...
The Instruction Set Architecure (ISA) of micro-processors is usually word oriented, so it is not optimized to perform bit level operations. A functional unit oriented to the bit manipulation could accelerate the computation increasing the microprocessor performance in terms of execution time. This work presents the experimental results of the integration between the Bit Manipulation Unit (BMU) described...
Advanced bit manipulation operations are not efficiently supported by standard microprocessors since they are optimized for fixed data size operations. In literature several hardware solutions are proposed to overcome this problem, and. In this work we present the experimental results of a new architecture based on LEON-2 and a simplified version of ADAPTO (Adder-based Dynamic Architecture for Processing...
In previous works ([1], [2] and [3]) the authors presented ADAPTO (adder-based dynamic architecture for processing tailored operators), a reconfigurable functional unit (RFU) that accelerates computations on data of shorter size than the native processor wordlength. ADAPTO is a reconfigurable array inserted directly in the data-path of the microprocessor in order to reduce the communication overhead...
Processing performance of algorithms implemented on conventional processors or DSP can degrade when bit level operations are involved. This degradation is related to the characteristics of logic and arithmetic operators present inside the processors, that are optimized for word level operations. Different methods have been proposed for overcoming this problem. A very interesting method is based on...
Microprocessor and DSP are optimized to perform operations on data having the same size of native wordlength. Their performances decrease when shorter data must be processed. In fact, operations on a short data have the same complexity native wordlength data and data resources are not fully exploited. Recently different solutions have been proposed to overcome this problem. Great attention has been...
Low cost microprocessors and DSPs are optimized to perform general arithmetic and logic operations on native wordlength. On the other hand, the efficiency decreases when they process shorter data (more clock cycles per operation are required). Recently different solutions have been proposed to overcome this problem. Among those, the one based on a main processor with a reconfigurable unit (RU) used...
Objective. To assess the accuracy of traditional weaning indices in predicting extubation failure, and to compare their accuracy when indices are measured at the onset of a breathing trial (SBT) and at the end of the SBT before extubation. Design. Prospective study. Setting. Medical-surgical intensive care unit at a tertiary care hospital. Patients. Four hundred eighteen consecutive infants and...
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