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The paper proposes a power supply unit to efficiently supply always-on or duty-cycled IoT loads which consumes in μW-range. This PS achieves the highest 93% and 99% current efficiencies at average output currents of 1μA and 100μA to date, respectively. This unit includes a voltage reference and oscillator to generate autonomously duty-cycled power delivery operation as low as a 30μ8 on-period. The...
This paper presents the behavioral modelling of a time domain signal conditioning circuit for resistive sensor. The architecture of the proposed circuit is based on a highly linear voltage-to-time converter circuit using injection locked oscillators as delay generators. A behavioral modelling based design approach is also presented in this paper. It facilitates the design in terms of time and complexity...
A novel resistive sensor interface for high temperature applications is presented. It is based on a time domain architecture using Injection Locked Oscillators as phase shifters that results in higher temperature hardness and simpler circuits. The system depends on the relative accuracy instead of its absolute properties and doesn't suffer from temperature variations. The proposed circuit is designed...
Increasing the number of bits per cell and technology scaling are ways to reduce the cost per gigabyte of flash memories and solid-state drives (SSDs). Unfortunately, this trend has a negative impact on data retention capability and cycling endurance. Periodic data refresh allows dealing with a reduced retention time and, indirectly, may be used to improve cycling endurance. A worst case data refresh...
In this paper, a highly linear voltage to time converter is presented. It can be used as a brick in the architecture of time-domain analog-to-digital converter. It is based on injection locked oscillators as phase shifter. The injection locked oscillator is implemented using a relaxation oscillator that has been chosen for its high linearity compared to other conventional architectures. The analog-to-time...
A new fractional frequency divider is presented. It is based on a random dithering of the phase error. The divider output spectrum is cleaned from any fractional spurious tone. Moreover, as no noise shaping is applied, the proposed solution can be implemented in frequency synthesizers like Phase Locked Loops (PLL) without implication on the loop filter.
A voltage-controlled oscillator (VCO) with a central frequency of 56 GHz and a 17% tuning range is presented. The oscillation frequency is tuned both by an analog input and by a 3-bit digital control bus using the same type of differential varactors. It achieves a record figure of merit, considering tuning range of 186.8 dBc/Hz and is able to address the full wireless high-definition multimedia interface...
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