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In this paper, a study on MOL (middle-of-the-line) RC performance and optimization of MOL resistance at both source/drain contact and local interconnect level at 7 nm node is presented. We focus on the device delay from 10 nm node to 7 nm node using a single stage driver circuit. The device delay is calculated based on a real 10 nm FINFET device. Then the result is compared with a shrunk version of...
In this paper, the impact of gap-fill planarity on Multi-Self-Aligned Block, SADP (self-aligned double patterning) process for advanced optical technology nodes (7 nm/5 nm) interconnects was studied through process emulations. This study specifically focuses on the insertion of an etch stop layer (ESL) between two coatings of organic planarization layer (OPL), referred to as the tri-layer PM (pattern...
In this paper, a strategy of performing segment removal in an SAQP (self-aligned quadruple patterning) and its implication on interconnect parasitic capacitance are reported. In order to reduce the cost and process complexity, through process emulations, this study specifically focuses on not introducing additional lithography step(s) or material to the conventional SADP (self-aligned double patterning)...
Integration of high porosity low-k dielectrics faces major challenges as the porosity weakens the dielectric, resulting in severe plasma induced damage (PID) and difficulties in profile control. Post porosity plasma protection (P4) integration strategy addresses those challenges by strengthening the dielectric via porosity refill during the integration steps. Realization of P4 integration at an advanced...
In this paper, major challenges for 5 nm node BEOL performance are presented. High wire resistance is a key issue for interconnect delay. Accordingly, we focus on potential wire resistance reduction with various architectures and materials. Copper liner thickness was identified as the major knob for increasing Cu areal percent, as compared to increased line aspect ratio and width. Interconnect delay...
In this paper, optimization of 1X BEOL wiring level of 7 nm node is presented. We focus on the interconnect delay from 10 nm node to 7 nm node using a single stage driver circuit. The device delay is calculated based on the characteristics of the 10 nm driver circuit. Then the result is compared with a shrunk version of the circuit at the 7 nm dimension. Therefore, the impact of the BEOL on the circuit...
In the attempts to push the resolution limits of 193nm immersion lithography, this work demonstrates the building of 3 metal level 56nm pitch copper dual-damascene interconnects, using Negative-Tone Development Lithography-Etch-Lithography-Etch (LELE) Patterning at line level.Line Resistance and intra-level capacitance can be affected by the double patterning integration, but a good process window...
This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) scheme where the local interconnects are with double pitch split in each direction, respectively. This scheme will provide great design flexibility for the...
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