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This paper proposes a novel population count circuit for Associative Memories (AM)s. Currently, AM chips requires a large number of silicon area for the population count circuitry. For this reason, is necessary an optimization in terms of area for the future AM devices to have a better memory density. A population count circuit counts how many blocks of the AM are in a matching state. If the count...
we present a system architecture made of a motherboard with a Xilinx Zynq System on Chip (SoC) and a mezzanine board equipped with an Associative Memory chip (AM). The proposed architecture is designed to serve as an accelerator of general purpose algorithms based on pipeline processing and pattern recognition. We present the open source software and firmware developed to fully exploit the available...
In this paper we present a new Associative Memory (AM) chip designed in the 28 nm TSMC HPL technology. Two of the main characteristics of the new chip are reduced power consumption and an increased memory cell area density by the use of two newly designed memory cell technologies. The aim of the new chip is to test the new technologies with realistic front-end functions. The integration of the AM...
This paper presents the design of a LVDS input/output interface circuit for the next generation of Associative Memory (AM) chip. The bandwidth of Associative Memories is a critical aspect that needs to be addressed in order to increase the number of comparisons per second. Our aim is to transfer parallel buses at 500 MHz. Since a large number of receivers/drivers will be included in the AM chip, power...
Associative memories are massively parallel circuits which perform a parallel comparison between stored data and input data. When operated in parallel comparison mode, they require high current spikes (in the order of few amperes) at every clock edge, and the voltage drop due to current spikes can seriously affect the circuit operation. This paper proposes a method to enhance the power integrity,...
This paper presents an overview of the ATLAS Fast TracKer (FTK) processor, reporting the design of the system, its expected performance, and the current integration status. The FTK is an upgrade of the trigger system of the ATLAS experiment. The system is designed to reduce the event rate from the proton-proton collisions occurring at 40 MHz to about 1 kHz for the expected LHC luminosity (2 × 1034...
This paper proposes a methodology to design radiation-hardened ICs, suitable for space applications and high-energy physics experiments. The miniaturization of ICs has brought an increase of circuit logic errors due to radiation, also at ground level. The increased complexity of IC design due to technology scaling requires new tools to design rad-hard circuits. In this paper, we propose a design tool...
This paper proposes a new design method to enhance the radiation hardness of circuits for the next generation of pixel detectors in High Energy Physics experiments. The approach is based on Radiation Hardness By Design methodology to mitigate Single Event Effects. In particle detectors, front-end electronics opeates in an environment characterized by a high dose of radiation. We propose a set of digital...
In this paper we describe a Content Addressable Memory architecture designed in 28 nm CMOS technology and based on the 65 nm XORAM cell previously developed. The cell is composed by two main blocks: a 6T SRAM, and a 4T XOR logic gate. Each XORAM cell makes a bitwise comparison between input data and stored data. The memory is organized in 18-bit words, and all the 18 XOR outputs bits must have a low...
In this paper, we describe a new logic family based on a Double-Rail Redundant Approach, that we call D2RA. Each cell receives both the input bits and their negated values, and is made of two main blocks: the first one produces the output bit, the second one the inverted output bit. When a bit and its negated value have the same logic value, then an error occurred. In such a case, the two output bits...
This paper presents the design of a static RAM cell in 65 nm CMOS technology. A good level of radiation hardness against cumulative dose effects can easily achieved by using a 65 nm technology, as the oxide thickness is thin enough to provide intrinsic radiation hardness against total ionizing dose. Single event effects can be mitigated by using ad-hoc techniques. The SRAM is based on Dual Interlocked...
This paper presents the approach used to characterize an Associative Memory Chip (AMChip) designed for the trigger systems of high-energy physics experiments in the Large Hadron Collider (LHC) at CERN. Pattern recognition is performed with Associative Memories (AM). A dedicated integrated circuit has been designed, fabricated and tested to verify that the proposed solution meets area, speed and current...
The AMchip is a VLSI device that implements the Associative Memory function, a special content addressable memory specifically designed for high energy physics applications and first used in the CDF experiment at Tevatron. The 4th generation of AMchip has been developed for the core pattern recognition stage of the Fast TracKer (FTK) processor: a hardware processor for online reconstruction of particle...
This paper presents a charge pump voltage doubler for programming flash memories to be employed in space applications. The device has been designed in a commercial 180 nm CMOS technology using radiation hardening by design techniques. Radiation tests carried out on prototype samples demonstrate immunity to latch-up, and an adequate level of hardness with respect to total dose.
In this paper we describe a Content Addressable Memory (CAM) architecture based on a new custom cell, called XORAM. The cell is composed by two main blocks: a 6T-SRAM, and a 4T-XOR logic gate. Each XORAM cell compares the input data on the bit line with the data stored in the 6T-SRAM cell. The output matching bit is obtained by performing a NOR operation between all bits of the XORAM cells storing...
This paper presents the design of three static RAM cells, designed to be radiation hard. The memory cells are designed with three different approaches and layout styles. Three memory arrays, each of them made with a different cell, were designed and simulated to optimize the transistor sizes. The layout of the cells has been drawn, and parasitic elements were extracted to analyze their impact on circuit...
This paper presents a tool based on a two dimensional charge-collection simulation to study non-destructive single event effects in CMOS IC blocks. The interaction between the radiation particle and the p-n junctions is modeled at circuit level with a set of parasitic currents, which are injected into the nodes corresponding to the geometrical areas at or near the point where the particle hits the...
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