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This paper introduces CMOS/magnetic tunnel junction (MTJ)-based asynchronous single-track circuits for re-initialization free computing against power failures. In energy-harvesting applications, data processed might be lost due to frequent power failures, which usually requires the initialization phase after the power supply is recovered. To prevent the re-initialization for energy-efficient computing,...
Thermal management for three-dimensional integrated circuits (3D ICs) is becoming a crucial challenge. In this paper, we propose new cooling architectures using thermal sidewalls, interchip plates, and a bottom plate (thermal-SIB architectures) for 3D systems that have a power dissipation of several tens to a couple of hundred W/cm2 as a vertical addition. There are several types of sidewalls: cap,...
In this paper, we propose a task allocation method for multi-core systems with the Duplication with Temporary Triple Modular Redundancy and Reconfiguration (DTTR) scheme. The proposed method optimizes both performance and reliability by allocating copies of tasks (i.e., redundant tasks) based on the maximum parallelism of tasks in a give application. In the experimental results, we compare the average...
Several studies have been made on comparison between synchronous and asynchronous NoCs (Network-on- Chips). However, very few attempts have been made at fair comparison between synchronous NoCs designed by synchronous researchers and asynchronous ones designed by asynchronous researchers under the same functional specification using the same fabrication technology. In this paper, representative routers...
In this paper, we propose a task allocation method for multi-core systems based on the Duplication with Temporary Triple-Modular Redundancy and Reconfiguration (DTTR) scheme. The proposed method statically determines task allocation for given task graph and multi-core system model from task scheduling for fault patterns of cores. In the experiments, we evaluate the task allocation time and the overhead...
This paper explores a new dependable real-time task execution scheme for a many-core system. This scheme is based on duplication with temporary TMR and reconfiguration. Unlike a common scheme with several spare units, every processor core in our scheme is used for task execution. Thus, redundant processor cores contribute to both the reliability and performance of the entire system. We first show...
Since asynchronous circuits consume power only when activities actually happen, the conventional serial communication scheme where the embedded clock is always transmitted and the clock and data recovery (CDR) circuit is continuously working is very wasteful for connecting asynchronous circuit cores. This paper proposes a new serial communication scheme for asynchronous circuits where the power consumption...
In this paper, we propose a method to reduce clock skew among stacked chips by a clock distribution network with multiple source buffers (MSB CDN). The propagation delays to all chips that need a clock signal are tuned only in the chip with a clock source. The adjustment is done in accordance with the size and number of buffers. Receivers in the same conditions are placed on the other chips. The output...
This paper proposes an effective model for evaluating vertical signal propagation delay in through silicon via (TSV) based three-dimensional integrated circuits (3-D ICs). The capacitance model for on-chip interconnects is also proposed. All parasitic parameter values for an entire structure can be calculated by the closed-form equations. The delay model is constructed with the first- or second-order...
This paper proposes closed-form expressions of parasitic parameters in a silicon substrate that consider substrate contacts. In general bulk CMOS technologies, the standard cells with bulk (substrate and well) contacts or tap cells for bulk contacts are used in physical layout designs. As tap cell placement methods, there are dense random placements and sparse regular placements in cell rows vertically...
We have been developing an NoC (Network-on-Chip) based platform for a centralized ECU (Electronic Control Unit), where a many-core system functions as a set of several conventional automotive ECUs. The outcome of this research project has formed into an evaluation platform that includes a hardware board, a dependable task execution scheme, its support tool for Simulink programs, and a functionality...
We propose a model for coupling that considers substrate contacts between through silicon vias (TSVs) in bulk-CMOS technologies. The proposed model is compact but has reasonable accuracy for the dense substrate contacts in large-scale three dimensional integrated circuits (3D ICs). We describe the modeling for substrate contacts with the equivalent electrical circuit, discuss the impact of substrate...
QDI-model-based asynchronous circuits which contain differential domino logic (DDL) circuits are promising implementation against random delay variations. A physical DDL cell can represent all the family functions without extra gates since it is based on the dual-rail encoding. This paper proposes a physical DDL library which only contains 12 cells and three logical synthesis libraries for this physical...
Three-dimensional integrated circuits (3D ICs) provide a promising solution for overcoming delay/power problems of 2D ICs by stacking chips vertically. Signal propagation speed among the stacked chips is very important for 3D IC systems. We propose a simple model for analyzing the vertical signal propagation in through-silicon-via-based 3D ICs and discuss the impact of physical parameter variations...
This paper proposes multiple-clock multiple-edge-triggered multiple-bit flip-flops for designing simple and straight-forward asynchronous control circuits of the two-phase handshaking protocol. The proposed flip-flops have multiple clocks and multiple data inputs, and each data input can be stored in the flip-flop at both the rising edge and the falling edge of the corresponding clock. They can be...
This paper proposes a multi-chip NoC approach for implementing centralized ECUs. Unlike the conventional approach where ECUs and sensors/actuators are connected tightly, it has potential to implement efficient and reliable systems for automotive applications. Then, this paper reports our experience of implementing our first chip designed for the multi-chip NoC platform, and shows some experimental...
Network-on-Chip (NoC) is now considered to be a promising approach to implementing many-core systems and some real-time applications are executed on them. However, it has not yet been proven that on-chip networks can theoretically satisfy the hard real-time constraints. In this paper, we propose the worst-case performance models of on-chip networks which represent the upper bound latency between NoC...
This paper proposes dependable routing algorithms for multi-chip NoC platforms. In a multi-chip NoC platform, multiple NoCs are connected via off-chip links, and on-chip networks are seamlessly extended to a multi-chip network. Such platforms have several potential advantages in embedded systems with many cores, such as automotive control systems. One limitation of this approach is that the extended...
We propose a processor-level fault tolerance technique based on the Pair and Swap scheme to improve the dependability of network-on-chip based multiple processor systems where each processor core has its private memory. In the proposed scheme, two identical copies of a given task are executed on a pair of processor cores and the results are compared repeatedly in order to detect processor faults....
Network-on-Chip (NoC) is now considered to be a promising approach to implementing many-core systems. In this paper, we propose fully asynchronous on-chip networks which have improved tolerance against stuck-at-faults, aging degradation faults and transient faults, as well as potential of high performance. We have developed a dependable routing algorithm to detour a faulty router or a faulty link...
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