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Multi-rate (MR) simulation is necessary for a system which contains both large and small time constraints. In the traditional MR real-time simulation of MMC, only the MMC valves are implemented on FPGA with a small time-step, while the rest parts are implemented on central processing units (CPU) with a large time-step. This paper presents a fully FPGA based MR real-time simulation of two MMC terminals...
Real-time simulation is an important tool of validating the performance of the modular multilevel converter (MMC). By using the field programmable gates array (FPGA), MMC valves with hundreds of sub-modules and the large number of inputs and outputs can be simulated in real-time. In the traditional FPGA based real-time simulation, only the MMC valves are implemented on FPGA, while the rest parts including...
The detailed real-time simulation of MMC-based HVDC links is one of the most challenging tasks in power system validation today, requiring the combined use of CPU and FPGA technologies. The inclusion of surge arresters in the real-time fault tests further increases the difficulties because of the highly non-linear characteristics of such protective devices. In this paper, the OPAL-RT digital real-time...
In this paper, an FPGA based SAR extended object simulator is presented focused on backscattering coefficients computing. It is aimed to be used for hardware-in-the-loop SAR raw signal simulation with applications in UAV or other platforms SAR sensors test and assessment. This simulator is based on geometrical optics (GO) model and can work in real time. The GO algorithm is analyzed and implemented...
Industrial modular multilevel converter (MMC) controllers usually implement the sub-module (SM) capacitor voltage balance control (VBC) in field-programmable gate array (FPGA) boards. Conventional VBC methods need to sort out the capacitor voltages, where the sorting algorithm would become too complex to be accommodated in FPGA if the SM number is large. A sorting-less VBC optimized for FPGA implementation...
Modular multilevel converter (MMC) is a promising topology for medium and high power applications. The MMC system consists a large number of sub-modules (SMs), which take long time to simulate. In a real-time simulator, the MMC model is optimized to have a fast simulation speed for real-time applications, such as hardware-in-the-loop (HIL) tests. The methodology to evaluate model fidelity is important...
The modular multilevel converter (MMC) STATCOM removes the need for AC filter and transformer, has no DC bus fault hazard, and thus becomes a better option than a 2-level voltage source converter (VSC) STATCOM. An MMC can have hundreds of submodules (SM). The switches in the SM are controlled individually and the capacitor voltages have to be balanced. Therefore, the control and protection system...
Being the first five-terminal Modular Multilevel Converter (MMC)-based HVDC project in the world, the control and protection system must be validated under various operation modes as well as contingency at the factory acceptance test. This paper presents the configuration and performance of a hardware-in-the-loop (HIL) test platform that is based on a multi-rate real-time simulator using commercial-off-the-shelf...
Despite the rapid development of VSC-HVDC technology, the practical experience to operate modular multi-level converter (MMC) has not yet been sufficiently accumulated. Real-time simulation is one of the most efficient approaches to verify the control and protection (C & P) scheme under various contingencies. With the increasing number of sub-modules, the accurate simulation of the MMC-HVDC becomes...
This paper presents real-time simulation results of a 512-level modular multilevel converter (MMC). Using off-the-shelf computers and FPGA boards, the converter, including the 6 valves, 6 arm inductors and the transformer, is simulated with a time-step of 450 ns. Such a small time-step is required to ensure high accuracy when applying gating signals but also when observing fault conditions. Simulation...
This paper presents the dynamic performance test of a complete control and protection system for a Multi-terminal MMC HVDC system using hardware-in-the-loop (HIL) simulation. A novel HIL bench with a cost-effective input and output interface between the control system under test and the real-time simulator is introduced. Two critical test cases, namely the start-up of the MMC connected to islanded...
Recently, two Modular Multilevel Converter (MMC) projects are under construction in China. Since these are the first two multi-terminal MMC projects in the world and the controllers are sophisticated, a real time simulation platform becomes critical to enable hardware-in-the-loop (HIL) test and validation of the MMC controllers in various scenarios, before applying them in the field. This paper presents...
An approach to estimate the performance of FPGA architectures is proposed based on semi-supervised model tree algorithm. The proposed approach avoids synthesizing, mapping, packing, placing and routing, which are essential steps in a traditional flow to obtain the performance of FPGA. Thus it is time efficient while the performance predicted maintains quite close to the result obtained through the...
This paper proposes a new nonvolatile Dual Interlocked Cell (NV-DICE) storage element. The cell includes a DICE latch and four backup ferroelectric capacitors. It can perform store automatically when the power is off abruptly and has high tolerance to SEU. READ and WRITE operations in this cell were simulated by HSIM. Single Event Upset (SEU) of the cell were simulated by Sentaurus simulation tools...
The FPGAs (Field-Programmable Gate Array) are popular in hardware designs and even hardware/software co-designs. Due to the advance of manufacturing technologies, leakage power has become an important issue in the design of modern FPGAs. In particular, the partially dynamical reconfigurable FPGAs allow the latency between FPGA reconfiguration and task execution for the performance consideration. However,...
Complex signal of chaos is generated to use in secure communication. A new chaotic system is constructed by anticontrol of chaos based on Chen system, which is different from Chen system in the third nonlinear term. The system constructed in this paper combines with Chen system to form a switchable chaotic system. The switchable chaotic system can change its behavior automatism from one to another...
In this paper, a motion control IC for X-Y table using FPGA (Field programmable gate array) technology is presented. To alleviate the effect of unmodelled dynamics and cross interferences while two tables simultaneously motion, an adaptive fuzzy controller (AFC) is used in position loop of X-Y table to improve the motion tracking performance. In implementation, an FPGA embedded by a Nios II processor...
Based on the characteristics of the nonlinear Boolean functions operated in stream ciphers, a reconfigurable hardware architecture for these nonlinear Boolean functions is presented, which could be reconfigured many different structures to match for the functions, such as the nonlinear Feedback functions of shift registers and the nonlinear filtering functions. The architecture in this design has...
The dynamic reconfiguration technique based on FPGA (field-programmable gate array) can improve the resource utilization. The dynamic reconfiguration principles and methods are discussed. A remote dynamic reconfiguration scheme using Xilinx Virtex-II FPGA and SMCS Ethernet PHY (physical layer transceiver) is proposed. The hardware of system is designed with Xilinx Virtex-IIXC2V30P FPGA that embeds...
This paper presents an FPGA-friendly approach to tracking elephant flows in network traffic. Our approach, single step segmented least recently used (S3-LRU) policy, is a network traffic-friendly replacement policy for maintaining flow states in a Naiumlive hash table (NHT). We demonstrate that our S3-LRU approach preserves elephant flows: conservatively promoting potential elephants and evicting...
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