Multi-rate (MR) simulation is necessary for a system which contains both large and small time constraints. In the traditional MR real-time simulation of MMC, only the MMC valves are implemented on FPGA with a small time-step, while the rest parts are implemented on central processing units (CPU) with a large time-step. This paper presents a fully FPGA based MR real-time simulation of two MMC terminals. The FPGAs are decoupled by the stubline, and are parallelly simulated. Each FPGA is assigned with one MMC terminal, and its time-step can be flexibly chosen. The decoupled FPGAs can run asynchronously with their own model, which only communicate via the stubline without the synchro between them. Thus, the real-time simulation of a multi-terminal MMC-HVDC grid can be easily achieved while the accuracy of the simulation is also guaranteed. The real-time simulation results of the proposed methodology are provided.