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This paper describes the electrostatic discharge (ESD) failure caused by parasitic BJT in N-substrate process. The study of ESD failures in P-substrate process[1-3] has been a topic of increasing interest. Meanwhile N-substrate process, which may cause unexpected ESD failure, has hitherto received little attention. Through data analysis, unexpected ESD failure in N-substrate process may be attributed...
The clamped inductive turn-off failure of Silicon-on-Insulator Lateral Insulated Gate Bipolar Transistor (SOI-LIGBT) with multi-finger layout pattern is investigated in this paper. Firstly, the measurements of device failure under clamped inductive turn-off are discussed. Secondly, simulations are carried out to reproduce the failure by using Sentaurus TCAD. It is found that the failure origins from...
A novel high-voltage interconnection (HVI) structure with dual trenches for 500V SOI-LIGBT is proposed in this paper. Compared with the conventional dual trenches structure, the proposed structure features a shallow trench (T1) and a deep trench (T2) beneath the HVI. By employing the shallow trench (T1), the potential can easily penetrate into the deep trench (T2) and the total potential sustained...
High performance silicon IQ modulator is fabricated and used to demonstrate the first 56 Gb/s direct detected single-sideband DMT transmission over 320-km SMF. The required OSNR of 26.3 dB at BER of 3.7×10−3 was achieved.
A new 700 V tridimensional channel-lateral insulated-gate bipolar transistor (TC-LIGBT) structure on 1.5-\(\mu\) m-thin silicon on insulator (SoI) layer is presented in detail in this paper. There are numerous separated p-body cells located in the emitter region of the investigated TC-LIGBT, which can increase the efficient channel width, enhance electron injection, and attain a large current capability...
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