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The experimental comparison between relaxed and strained Ge pFinFETs operating at room temperature is discussed. Although, the strain into the channel improves the drain current for wide transistors due to the boost of hole mobility, the gate stack engineering has to be further studied in order to solve the threshold voltage shift. The relaxed channel achieves a lower subthreshold swing compared to...
We investigate for the first time the influence of the back gate bias (VB) in the main digital and analog parameters on Silicon-On-Insulator (SOI) omega-gate nanowire devices down to 10 nm width (W). For wider channel, it was observed that for high negative VB the subthreshold swing (SS) and DIBL are decreased due to the better channel confinement while the intrinsic voltage gain is almost insensitive...
The characterization of low-frequency (LF) noise is carried out in p-type Si passivated Ge FinFETs, comparing the performance of narrow (Wfin = 20 nm) and planar-like (Wfin = 100 nm) devices. The low-frequency noise is shown to be dominated by flicker noise, i.e., (1/fγ) where γ∼1, in the evaluated frequency range for both fin widths, which is governed by number fluctuations. Furthermore, narrow devices...
The goal of this work is to study parameters related to the analog performance of tunnel field effect transistors (TFETs). The obtained results have been analyzed in terms of temperature variation (ranging from 25°C to 150°C) and source composition (Sh-xGex and 100% Si). The first part is focused on characteristic curves of the drain current as a function of gate voltage and drain voltage. Next step...
The analog performance of hetero-junction vertical NanoWire Tunnel FETs (NW-TFETs) with different Ge source compositions (27% and 46%) is studied and compared to Si source devices. Although the NW-TFETs with the highest amount of Ge at the source present the highest transconductance (lower bandgap and higher BTBT predominance), the NW-TFETs with 27% Ge source present a better intrinsic voltage gain...
MuGFET devices show good gate-to-channel control, reducing short channel effects and increased current drive [1] and their performance can be improved through implementation of mechanical stress in the silicon fin. In th is wor k we study t he stress distr ibution and transconductance behavior in unstrained and biaxially + uniaxially strained tri-gate SOI nMOSFETs with different fin dimensions through...
The stress profiles extracted showed that the variation in the silicon fin dimensions influence the stress levels and distributions along the silicon fin. From the analog performance view, these variations in the stress have influence on some electric parameters. The reduction of the total fin length showed no significant change in the parameters, although a reduction in the stress level was noticed,...
In this work the proton irradiation influence on basic and analog parameters of triple-gate SOI MOSFETs is investigated. The studied devices are strained and unstrained p- and nMuGFETs. The type of stress considered in each case, was the stress that results in a better performance of p- (CESL) and n-devices (sSOI+CESL). Although the results showed the worse behavior for post-irradiated nMOS transistors,...
From the analog performance perspective, there is a fin cross-section shape influence on electric parameters. At weak inversion levels the gm/ID is shape dependent, while for moderate and strong inversions the strain type is dominant, where the mobility starts to play an important role. The output conductance and the Early voltage show a strong dependence on both fin shape and strain type. For thinner...
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