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Silicon based Physical Unclonable Function (SPUF), a chip level identifier that utilizes the inherent irregular manufacturing process variations, can be extended to Ring Oscillator PUFs (ROPUFs). The ROPUF structure, although promising for FPGA based platforms, is not area efficient in terms of response bit per RO circuit implementation. This paper introduces an area efficient Stage Configurable ROPUF...
In this paper, we aim at increasing the strength of weak arbiter physical unclonable function (APUF) which are vulnerable to modeling attacks because of low uniqueness and randomness. We propose a unique technique which takes n × 1 challenge-response pairs (CRPs) from APUF and combines them with ring oscillators (ROs) implemented on the same FPGA to get n × n CRPs. We claim the proposed technique...
Physical Unclonable Functions (PUFs) are the state-of-the-art topic in hardware oriented security and trust (HOST). PUFs have recently emerged as a promising solution for cyber security related issues including low-cost chip authentication, hacking of digital systems and tampering of physical systems. In this paper, a dynamic area efficient design along with an algorithm, namely, Optimal Time Delay...
Security issues pertaining to Advanced Metering Infrastructure (AMI) system has been a major concern since the advent of the smart grid. In this paper, a novel authentication and key management scheme is proposed for AMI system based on Configurable Ring Oscillator Physically Unclonable Functions (RO PUFs). The scheme provides end-to-end security for the confidentiality and integrity of messages exchanged...
Physical Unclonable Functions (PUF) offer promising solution to security problems. A PUF is a die-specific random probabilistic function that is unique for every instance of the die. PUFs derive their randomness from the uncontrolled random manufacturing process variations in the IC. Apart from spatial variation or process variation, ICs are affected by temporal variation. In this work, we study the...
In this paper, a configurable ring oscillator PUFs (c-ROPUFs) is utilized to improve PUF entropy and reliability. In addition, a novel security technique to enhance PUF's reproducibility using a newly defined parameter namely intra-die diverseness is introduced. An implementation of c-ROPUF on a Xilinx Spartan-3E FPGA on 30 different chips under different environmental conditions is shown. Experimental...
Silicon Physically Unclonable Functions (SPUFs) are delay based PUFs that exploit stochastic manufacturing process variations of Integrated Circuits (ICs) on silicon chips to construct unclonable cryptographic secret keys which are unique for each chip. One variant of SPUFs, named Ring Oscillator (RO) PUFs, is typically used for the authentication of silicon technology devices including FPGA chips...
Physical unclonable functions (PUFs) are security features that are based on process variations that occur during silicon chip fabrication. As PUFs are dependent on process variations, they need to be robust against reversible and irreversible temporal variabilities. In this paper, we present experimental results showing temporal variability in 4, 5, and 7-stage ring oscillator PUFs (ROPUFs). The...
Malicious inclusion inside integrated circuits (ICs) is a recently evolved concept in the semiconductor industry. This has become a matter of concern with the increase in outsourcing of semiconductors which are used both in military and commercial sectors. To facilitate the detection of Trojans using power based analysis, NOT gate based ring oscillator (RO) network models have been suggested in the...
Physical unclonable functions (PUFs), are physical entities that are embodied in a silicon chips and can be easily evaluated but they are difficult to predict. Ring Oscillators (ROPUFs) are appropriate security techniques for FPGA-based systems. This paper presents a Configurable design of ROPUF controlled with programmable XOR (PXORs) gates for area efficiency and stronger secret key production....
As FPGAs move into nanometer regime CMOS technology, new performance and lifetime limitations have started showing up. The process variation effects cause undesired behavior of the circuit as transistor dimensions decrease. This work makes an effort to understand the importance of routing in FPGAs and its impact on the performance of nanometer scale FPGAs. Lifetime failure of FPGAs can be detected...
Majority gates are fundamental logic gates that can be implemented in several potential post-CMOS technologies such as Quantum-dot Cellular Automata, Single Electron Transistor, and Tunneling Phase Logic. It is expected that these technologies provide more dense circuit integration levels than current CMOS technology. In this paper, a review of existing synthesis techniques targeted for majority logic...
The reduction in the transistor and interconnect dimensions have a severe impact on the reliable performance of the Field Programmable Gate Array (FPGA) circuits. The process variation effects in nanometer scale technologies result in transient errors or permanent failures that cause undesired behavior of the circuit. In this work, we analyze a method for fault identification to mitigate the impact...
Physical Unclonable Function (PUF) is a function that cannot be modeled as it utilizes the random process variations on a silicon chip to generate a unique bit stream of ‘1’s and ‘0’s (response bits) which can be used for authentication and cryptography applications. As PUF is highly rely upon process variations, the response bits generated are governed by the systematic process variation instead...
The wide use of Field Programmable Gate Arrays (FPGAs) in critical applications including, military and airborne applications require fault free operation of the FPGA. In FPGAs, faults can occur in the memory resources, logic blocks, or the interconnects. In this paper, memory faults including Stuck-at, Transition, Address Decoder, Incorrect Read, Deceptive Read Destructive, and Data Retention Faults...
Hardware security in Field Programmable Gate Arrays (FPGAs) which use Physically Unclonable Functions (PUFs) rely on the ability to produce a large number of unique frequencies. This paper explores the frequency uniqueness as it relates to the number of stages used to build a ring oscillator. The experimental results from Xilinx Spartan 2 FPGAs show that the three stage ring oscillators have the highest...
This paper describes a technique that exploits the process variation in Field Programmable Gate Arrays (FPGAs) in order to generate varying frequencies using asynchronous ring oscillators. To study its feasibility, Physical Unclonable Functions (PUFs) are implemented on FPGAs for generating unique signatures based on different frequencies generated from oscillators. The variation in frequencies generated...
New technologies such as Quantum-dot Cellular Automata (QCA), Single Electron Tunneling (SET) and Tunneling Phase Logic (TPL) have been proposed as alternatives for CMOS technology. These technologies are based on the use of majority/minority logic. Existing logic synthesis methods targeting majority/minority logic based on three-feasible networks often result in non-optimal solutions. In this paper,...
This paper presents a novel design of a Field Programmable Gate Array (FPGA) based on Quantum-dot Cellular Automata (QCA) technology. QCA is a transistorless emerging technology based on Coulombic repulsion. It is being explored as one of the alternative technologies which may replace CMOS in the future. In this work, QCA based nano FPGAs are designed and simulated. The designs of the Configurable...
The threat of digital counterfeiting and forgery of integrated circuits is growing at an alarming rate. At the same time, the functionalities of integrated circuits are becoming much more complex. This paper presents a design for cryptographic applications using Physically Unclonable Functions (PUFs) that can be implemented on an FPGA taking advantage of its unique architecture. The first part of...
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