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A low power and low phase noise phase-locked loop (PLL) is proposed in this paper to provide a quadrature millimeter-wave source for the 60GHz direct-conversion transceiver. An in-phase injection-coupled quadrature voltage controlled oscillator (IPIC-QVCO) [1] whose symmetric coupling structure is composed of four diode-connected transistors is implemented to optimize both phase noise and phase error...
In this paper, a fully integrated 24GHz integer-N PLL for a 60GHz wireless transceiver is presented. A VCO with tail-feedback technique is used to improve the phase noise by modulating the tail current, and a switched varactor array is also adopted together with a switched capacitor array to compensate the variation of KVCO over different bands. Moreover, benefiting from the careful optimization of...
A fully integrated phase-locked loop (PLL) frequency synthesizer for WLAN applications is designed in a 0.13-µm CMOS process. In order to make the loop bandwidth constant across the whole operating frequency range, a switched varactor array based LC-VCO is used to achieve a low KVCO variation, the charge pump current is programmed proportional to division ratio, and the variation on LPF resistance...
A dual-mode ultra-wideband VCO designed in a current-reused configuration is presented. By changing the coupling mode of the transformer tank, an ultra-wide frequency tuning range is achieved, while the current-reused topology is also incorporated to further lower the dc power consumption. Optimized in 90-nm CMOS technology, the proposed VCO attains a tuning range of 96.8% from 2.15 to 6.18 GHz, while...
The 802.11ac WLAN standard can provide wireless throughput up to several Gbps by employing wide signal bandwidth, high-order modulation, and multi-user MIMO. However, these new physical layer characteristics bring significant challenges in RF transceiver design. In this paper, system-level simulation platform based on 802.11ac standard is constructed, and error vector magnitude (EVM) degradation due...
A 24-GHz fully integrated integer-N phase-locked loop (PLL) is presented in this paper. Benefiting from the bias noise filtering technique, the voltage controlled oscillator (VCO) in the loop achieves a low phase noise. Moreover, the supply voltage of VCO is as low as 0.8-V due to the low-threshold-voltage transistors used in the design. The proposed PLL is fabricated in 90-nm CMOS technology. The...
A wide tuning range 24GHz VCO (voltage-controlled oscillator) using IBM 90nm CMOS process is presented. Switched inductor and two bits capacitance array offer a widely tuning range. In addition, optimized switches are adopted to improve both tuning range and phase noise performance. Simulation shows that -101dBc/Hz phase noise is achieved at 1MHz offset. The tuning range of the VCO spans from 21.9GHz...
A low phase-noise 24GHz VCO (voltage-controlled oscillator) for mm-wave WLANs (wireless LANs) using IBM 90nm CMOS process is presented. A current source is used to minimize the impact due to the process variation. Biasing filter technique is adopted to improve the phase noise performance. In addition, optimized switches are proposed to prevent phase noise degradation. Simulation shows that -101dBc/Hz...
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