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This paper investigates the failure mechanism of Ultra High Voltage JFET (UHV-JFET) under Unclamped Inductive Switching (UIS) test. We explain the ruggedness failure of the Power MOSFETs based on drain impact ionization event, diffusion current flowing through the impact ionization area enhancing the impact ionization level. An optimum drain engineering technique based on device structure and implantation...
A novel N-JFET structure, combined with an innovative control gate between the uniform P-top and source is proposed. Control gate has a heavily doped P-type and a gap to uniform P-top. Pinch-off voltage of the JFET device can be easily adjusted by the size of the gap, while the breakdown voltage can be kept in the range of 700V ∼ 800V. Rather than using 3D simulation which is more time consuming,...
Behavior of doping profile will affect the device performance dramatically as shown in this work. To get better prediction accuracy on device simulation, calibration based on electronic stopping power adjustment is applied on Taurus Monte Carlo implantation model according to Secondary Ion Mass Spectrometry (SIMS). Well determined particle number of calibrated Taurus Monte Carlo is used to simulate...
This paper presents the effect of side diffusion and doping concentration profile produced by two different ion implantation model for UHV LDMOS device with Linear P-top and its effect on device performance. The result shows that the device using Monte Carlo Model have different side diffusion with different N-Epi layer background whereas Taurus Table is unable to explain the side diffusion and Monte...
In this paper, low cost 1200V UHV LDMOS device has been proposed. As BVD and Ron are contradictory, so to make low Ron, high breakdown voltage is the challenge of this paper. The key feature of this device is the linear P-top which is used to obtain best charge balance, and increase the diffusion current to move faster in the drift region which reduces the electric field and substantially helps to...
This paper presents an innovative 500V LDMOS device is constructed by SCR structure, a thin oxide and poly resistor. This structure can improve the self-protection capability of LDMOS for Electrostatic Discharge (ESD), because this structure can distribute current from the drain to the poly resistor, so the transistor effect occurs earlier. After sequential ESD zapping applied on this device, lattice...
Simulation tools are very important to develop process and design a new device structures. Device characteristics and physics phenomena also can be analyzed and predicted using this tools. High energy implantation of dopant atoms is used to form buried layers of high conductivity in silicon. These layers have many potential applications. In order to make optimum use of very high energy dopant implants,...
An innovative and improved UMOS device structure, with gate oxide 900 to 1500A, breakdown voltage 40 to 100V, robust to hot carrier injection (HCI) stress is proposed. We demonstrate and report the effect of p-type and n-type doping in gate oxide and poly-gate region can improve HCI performance significantly. The UMOSFETs HCI, response to doping in the gate oxide and poly-gate is been studied.
In this work, a trench power MOSFET (UMOS) with vertical RESURF is investigated. And the influence of some key parameters on UMOS static performances are simulated and analyzed by TCAD-Process. The proposed RESURF conventional trench gate UMOS is able to achieve better UIS performance while maintaining a specific low on state-resistance with breakdown voltage over 100 Volts. Here we are proposing...
An innovative and improved UMOSFET device with low specific on-resistance maintain desired breakdown voltage up to 100V. In this proposed device, p-pillar under the p+ region UMOS structure has been developed and successfully simulated by using 2D simulation. The proposed structure can reduce the electric field near the trench gate UMOSFET. The trench gate with p-pillar increase the drift region doping...
A 600–800 V, BCD technology platform is presented in ultra-high voltage applications. An innovative feature is that all the devices have been realized by using a fully implanted technology in a p-type single crystal without an epitaxial or a buried layer. Ultra-high voltage triple RESURF LDMOS with the breakdown voltage up to 600–800V as well as low voltage CMOS and BJT have been achieved using this...
In this paper, a novel 60V multiple RESURF lateral double-diffused MOS (LDMOS) transistor with shallow trench isolation (STI) in unit cell and double cell structure has been developed and successfully simulated. The proposed multiple RESURF LDMOS is able to achieve a benchmark on-resistance of 26 mΩ-mm2 while maintaining a breakdown voltage of above 60 volts. The key feature of this novel device structure,...
In this paper, a normal nano-sensor technology using "top-down" poly-silicon nanowire field-effect transistors (FETs) in the conventional Complementary Metal-Oxide Semiconductor (CMOS)-compatible semiconductor process. The nanowire manufacturing technique reduced nanowire width scaling to 50 nm without use of extra lithography equipment, and exhibited superior device uniformity. These n...
Electrostatic Discharge (ESD) has become one of the most critical reliability issues in integrated circuits (ICs). The number of circuit design iteration due to electrostatic discharge (ESD) failures increases with the complexity of VLSI technologies and their shrinking. In this paper, we show how TCAD simulation and ESD macro-model can be used to solve ESD protection issues in GGNMOS (Gate-Grounded...
A new double integration-based method to extract model parameters is applied to experimental polysilicon nanowire MOSFETs. It was experimentally found that the saturation current shows the sensitivity of the Nano-wire MOSFETs if the conventional method fails to show the sensitivity depending upon the threshold voltage of Nano-wire MOSFET. It shows that the present method offers advantage over previous...
The growth rate of epitaxy depends primarily on parameters such as source gas deposition temperature pressure and concentration. Most microelectronic circuits fabrication that use epitaxial wafers require a lightly epitaxial layer (1014–1017 atom/cm3) on a heavily doped substrate (1019–1021 atom/cm3). The distribution of vacancies and interstitials is important for the distribution of the high surface...
In Complementary Metal Oxide Semiconductor (CMOS) process, isolation is the key and it has got more influence on the device performance. The most advanced process is using Shallow trench isolation (STI) technology, but for small geometry processes using STI technology will be very difficult because of severe HCI (Hot Carrier Injection) problem and need to have new advanced equipment for using STI...
This work investigates the degradation of electrical characteristics of amorphous silicon thin-film transistors during the accelerated ESD stress with a 40V high voltage and a high/low current of 2 mA/0.1 μA conditions. Both the leakage current and the threshold voltage shift are severe as the accelerated ESD stress applied at the gate region. The 40V accelerated ESD stress with a high current has...
This paper investigates a relatively new photoresist MR-I 7010R for its use in thermal nanoimprint lithography. The primary aspects tested were the thickness of the photoresist post imprinting and uniformity of the resulting residual layer thickness (RLT). These aspects were determined with respect to the initial thickness of the photoresist, which was deposited via spin-on coating, and change in...
In this paper an Hspice macro model is presented to model the snapback characteristics of GGNMOS (gate-grounded NMOS) and GCNMOS (gate-coupled NMOS) under ESD stress. The 5V NMOS be simulated in this paper is based on the 0.35um BCD technology as an ESD protection device. The new macro model has successfully predicted the trigger voltage and holding voltage of the GGNMOS and GCNMOS according to the...
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