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A temperature estimation method is proposed which utilizes the ratio of two emitter-to-base voltages of bipolar transistors. This removes the need for a precision reference voltage from the digitization step by implicitly implementing the reference in the digital backend. Using measurement data for p-n-p transistors in a 65-nm CMOS technology, we show that the proposed scheme is tolerant to tens of...
This session presents multiple SAR-based ADC designs and one pipeline ADC. Various novel circuit techniques for residue amplification are demonstrated using auto-zeroing, positive feedback regeneration, voltage-to-time conversion, and ring amplifiers. Moreover, the robust application of SAR converters in high-speed applications is demonstrated with time-based sparkle-code correction and DSP calibration.
Beamforming is used to correct for phase or time delay in signals received at multiple antennas in mm-wave receivers. The correction is meant to improve the signal-to-noise ratio and the bit-error-rate (BER) by filtering away the effect of noise and interferences. Typically, phase-corrected beamformers are used for lower fractional bandwidth applications, where the symbols are well spaced. In wideband...
Weight measurements are part of current medical care for congestive heart failure (CHF) patients. In this work, we explore the potential of shoe-mounted pressure sensors to automatically and remotely estimate the weight of CHF patients. We show that weight estimation accuracy degrades due to human subject movement. Moreover, we show that for a standing human subject the accuracy is influenced by the...
This brief presents a SAR ADC based design for on-chip temperature sensing which does not require an explicit voltage reference. Instead, the reference is implemented digitally using only the inputs from the sensor. We demonstrate two novel approaches to implicitly implement the reference: polarity-based and ratio-metric based approaches. Simulation results in 65nm CMOS for a 12-bit ADC demonstrate...
A flash-TDC hybrid ADC architecture is proposed in this paper. The operating principle relies on measuring the impact of the input amplitude on the delay of the comparators in the flash. TDCs capture this timing information, which is mapped to an output digital code using simple digital logic to provide additional bits of resolution.
The most common operation of an IoT sensor is that of short activity bursts separated by long time intervals in sleep or listen modes. During the data bursts, sensed information has to be reliably communicated in real time without draining the energy resources of the sensor node. One way to save such resources is to efficiently code the data burst, use single-channel communication, and adopt ultra-low-power...
In wireless communication systems, multipath and interference effects degrade the SNR and increase the BER of received signals. Antenna arrays and beamforming algorithms are typically used to improve system performance and noise immunity. For non-adaptive beamforming where signal-path gains remain unchanged, power dissipation is predictable but SNR and BER depend on the changing statistics of the...
A LC ladder based lowpass filter and programmable gain amplifier is presented for the baseband section of a mm-wave wireless receiver. The filter design combines buffering, filtering and termination in a single stage. Implemented in 180nm CMOS and occupying 0.36mm^2 area, it's measured lowest and highest gain settings are 5.6 and 21.6dB, with corner frequency of 2.3GHz and 1.76GHz, IIP3 of 13.9 and...
An important synchronous circuit element in low-power digital circuit design is the voltage level shifter at the boundary between voltage domains. In this paper, we present a full variability analysis of an optimized, synchronous pulsed half-latch level converter (PHLC) in the GLOBALFOUNDRIES 28nm technology. The variability analysis clearly illustrates the impact of ultra-low-power design on delay,...
This paper introduces a time-interleaved (TI) analog-to-digital converter architecture that exploits the correlation between consecutive samples. Two predictive algorithms, i.e. the last sample prediction and linear extrapolation prediction, have been investigated. Simulation results show that for a filtered random or modulated sequence sampled at an oversampling ratio of 4, both algorithms perform...
A low-power continuous-time ΔΣ ADC for HSDPA (High-Speed Downlink Packet Access) applications provides 83 dB dynamic range and 1.92 MHz bandwidth. A high sample rate (245.76 MHz) and an FIR filter in the outer feedback path minimize susceptibility to jitter. A TIA-based integrator with direct connection of inner feedback DAC current sources to integration capacitors supports the high sample rate....
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