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In this paper, we developed a high-level simulation model for DRAM controllers to capture such features as burst alignment, scheduling policies, etc. The model is based on SystemC/TLM for ESL platform integration. Compared to a commercial RTL implementation, the model has a worst-case error of 4.5%. Due to its fast simulation speed, we then apply the model to demonstrate two design trade-offs. The...
We present a novel design of scalable many-core processor with its comprehensive development framework, including the Electronic System Level, Register Transfer Level, and full-system prototyping platforms. Architecture exploration, performance evaluation and system verification/validation can be done across different abstraction levels. With our hardware-independent software layer, applications built...
Network-on-chip (NoC) can be a simulation bottleneck in a many-core system. Traditional cycle-accurate NoC simulators need a long simulation time, as they synchronize all components (routers and FIFOs) every cycle to guarantee the exact behaviors. Also, a NoC simulation does not benefit from transaction-level modeling (TLM) in speed without any accuracy loss, because the transaction timings of a simulated...
Process variation in advanced CMOS processes is an increasingly important influence in test efficiency, design optimization and yield learning. Yet, there is no efficient test process to assist designers to categorize chips for analyzing the influence of variation on their respective objectives. In this paper, we propose a test process and an analysis method with multiple clocks. Each chip is first...
Developing embedded parallel applications efficiently in modern single-chip many-core architectures is challenging. We present a novel methodology to facilitate crucial issues of parallel software development such as performance evaluation, speedup and bottleneck analysis, and system verification by taking the advantages of exploring many-core platforms in different abstraction levels altogether....
Process variation comes from several aspects during IC manufacturing, resulting in tremendous yield loss in advanced CMOS process. Recently, post-silicon tuning techniques that could adaptively manipulate failed chips to compensate the variations have been widely studied. Yet, full-chip adjustments can also increase dynamic and leakage power consumption. A fine-grain voltage-control architecture was...
We present a design of many-core processor architecture with superior cost-effectiveness to fulfill the rapid increasing demand of high-speed embedded multimedia applications. The prototype platform consists of sixteen processor cores and a 4-by-4 mesh-based duplex network interconnection with external memory. The hardware and software interface in a bare-metal environment, i.e., without an Operating...
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