The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In order to be able to handle an arbitrary amount of static communication segment faults in NoC-based MPSoCs, a flexible fault tolerance mechanism has to be applied. In this contribution, we present a flexible and scalable approach for fault-tolerance in NoCs, which - in contrast to existing circumvention techniques - can in principle handle any number of static faults in the routing network. It doesn't...
3-Dimensional Networks-on-Chips (3D NoCs) are proposed as the next generation interconnect infrastructure for multi/many core embedded systems due to the high performance characteristics and scalability. However the heat and thermal issues in 3D NoCs are critical. Reducing the vertical links between dies becomes can be one of the proper solutions, but the 3D NoC system performance can be harmed due...
Network-on-Chip (NoC) is proposed as the next generation interconnect technique for multi/many core embedded systems due to the high performance and scalability. An efficient and correct emulation method is significantly important for NoC system design and verification. In this paper, we would like to present a formalized and efficient hardware/software co-design method to emulate NoC system design...
In this paper a new latency analysis method for wormhole switched Networks-on-Chip is presented. This method can be used for many wormhole switched NoC with flit interleaving and static routing. The latency estimator is intended to be used for a fast performance estimation and evaluation processes where a simulation is too computationally intense. This could especially be used for optimization problems...
3-Dimensional Networks-on-Chip (3D NoC) have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoCs) interconnect. Due to the cost in terms of thermal, yield, chip area and design complexity, minimizing the number of Through-Silicon-Via (TSVs) in 3D ICs has become on the most important design issues. In this paper, we will...
As the embedded system design focus moving from computation-centric to communication-centric, Networks-on-Chip (NoCs) have been selected as the next generation interconnect components for multi/many core systems due to the scalability and high bandwidth. However, the NoCs design has reached the bottleneck in terms of power consumption, data communication latency and chip area nowadays. 3D chip technologies...
The advantages of moving from 2-Dimensional Networks-on-Chip (NoCs) to 3-Dimensional NoCs for any application must be justified by the improvements in performance, power, latency and the overall system costs, especially the cost of Through-Silicon-Via (TSV). The trade-off between the number of TSVs and the 3D NoCs system performance becomes one of the most critical design issues. In this paper, we...
3D ICs have emerged as the promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoC). Along with the advantages, it also imposes lots of challenges in terms of cost efficiency, technological reliability, power, thermal budget and so forth. Networks-on-chip (NoC) is thoroughly investigated in 2D SoC design as scalable interconnects, is also...
3D integrated circuit (IC) technology can be applied to the already known 2D Network-on-Chip (NoC) approach for System-on-Chips (SoCs). This resulting new approach brings advantages like higher integration density and better performance but also raises the question when the higher implementation costs are really profitable. To answer this question, for a lot of different cases, a framework was developed...
3D ICs have emerged as promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes lots of challenges in terms of cost, technological reliability, power, thermal budget and so forth. Networks-on-chip (NoCs), which is thoroughly investigated in 2D SoC design as scalable interconnects, is also well...
3D ICs are emerging as a promising solution for scalability, power and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes a number of challenges with respect to cost, technological reliability, thermal budget and so forth. Networks-on-chip (NoCs), which is thoroughly investigated in 2D SoCs design as scalable interconnects, is also well relevant...
Today industry is moving towards Multi-Processor Systems on Chip (MPSoCs) to take advantage of available parallelism. But common bus architectures for MPSoCs are not suitable as communication infrastructures, due to significant reduction in system throughput. To solve this problem, many Networks-on-Chip (NoCs) architectures have been proposed and analyzed extensively with respect to latency, area...
The rapid improvement of semiconductor technologies is the enabling factor for the design of large-scale System-on-Chip (SoC) architectures. At the same time the scale-down of feature sizes in silicon technologies brings up new challenges as parameter variations of the transistor devices, an increased vulnerability for wear-out effects during the lifetime of the device and increased sensitivity for...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.