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A power-rail electrostatic discharge clamp circuit with transient and static hybrid-detection enhanced triggering is proposed in this work. By skillfully co-optimizing the driving paths of both transient and static detection networks, the proposed circuit achieves a clamp device transient response time over 2 times longer than its RC time constant, which endows the proposed circuit with both promoted...
Transient behaviors of the diode-triggered silicon controlled rectifiers (DTSCRs) under very-fast transmission line pulse (VF-TLP) testing are investigated in this paper. The underlying physics needs to be comprehensively investigated and 2D/3D device simulations are well performed and compared. Analysis uncovers that the turn-on process of intrinsic SCR is ascribed to Darlington effect as well as...
Electrostatic discharge (ESD) protection circuits are often designed with detection circuits to trigger clamp devices to bypass ESD currents. In order to fully characterize performance of these protection circuits, a wafer-level characterization method is proposed in this work. By separating the detection rail from the supply rail, triggering actions resulted from detection circuits can be clearly...
This work presents a novel power-rail electrostatic discharge (ESD) clamp circuit for nanoscale applications. By skillfully incorporating transient and static ESD detection mechanisms into its detection circuit, the proposed circuit achieves a wide range of adjustable triggering voltage (Ft1) while maintaining low standby leakage current (Ileak). Besides, the proposed circuit achieves significantly-improved...
A novel on-chip four-bit transient-to-digital converter with a single RC-based detection for system-level electrostatic discharge (ESD) protection design is proposed in this paper. The proposed transient to digital converter is designed to detect ESD-induced transient disturbances and transfer different ESD voltages into digital codes under system-level ESD tests. This work is simulated in a 65-nm...
A novel power-rail ESD clamp circuit with a small time constant to achieve a longer turn-on time is proposed. During an ESD event, the turn-on time of discharge transistor Mbig in the proposed circuit is 5.87 times of that of the traditional one; under the normal power supply condition, the total leakage current has reduced to 4.635% compared with the leakage current of traditional circuit; under...
A novel input ESD protection circuit design is proposed in this paper. Voltage amplitude detection components are added into the novel design to effectively isolate gate oxide of input receiver from input pad to avoid voltage overshoots damage in ESD events while negligible signal degradation is maintained in normal data transmission.
A novel dual-directional silicon controlled rectifier (dSCR) device with dummy gate for electrostatic discharge (ESD) protection is presented. Compared with the traditional dSCR, the novel device has the desirable characteristics of dual-directional conduction, a low ESD trigger voltage, an adjustable ESD holding voltage and non-consumption of the extra area.
A novel symmetric n-type lateral diffusion MOS (sym-nLDMOS) is presented. Fabricated without any extra mask in a standard 0.18µm 60V SOI BCD process, the new sym-nLDMOS has an ability of electrostatic discharge (ESD) self-protection. The TLP measured results show about 1X improvement of It2 in the novel sym-nLDMOS. The output characteristics of the novel device are also be measured.
A power clamp circuit using current mirror is proposed in this article. The current mirror is used for capacitance multiplication in the proposed circuit. Besides, the proposed circuit has different turn-on and turn-off paths towards clamp transistor and it employs a non-traditional phase inverter in the turn-on path of clamp transistor. Simulation results verify that the proposed circuit has enhanced...
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