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Many analog and mixed signal devices have very few or no digital pins. In spite of this, these products can be highly complex internally, including significant digital content. They may contain various sensors and control circuitry, which react to a variety of conditions to control the power profile of the part and its environment. These factors can make these devices very challenging to test. They...
Despite the success of IEEE 1687, it has one significant shortcoming: it's difficult to use on devices without an 1149.1 test access port controller. IEEE P1687.1 addresses this problem.
This work presents a case study of wafer probe test cost reduction by multivariate parametric testset optimization for a production RF/A device. More than 1.5 million tested device samples across dozens lots and hundreds of parametric measurements are analyzed using a new automatic testset minimization system. Parametric test subsets are found that can be used to predict infrequent wafer probe failures...
Non-robust tests for path delay faults (PDFs) have gained importance in industry as a high percentage of PDFs are non-robustly testable in comparison to robustly testable PDFs. In this paper we present a novel function-based method to generate test patterns for the non-robust testable PDFs under the launch-off-capture (LOC) scan architecture. In contrast to a recently proposed function-based method...
This paper presents a novel function-based test generation technique for path delay faults (PDFs) under the launch-off-capture (LOC) scan architecture. The LOC architecture imposes the condition that the second test pattern must be a functional response of the initial scan test pattern. The proposed function-based LOC methodology incorporates traditional function-based ATPG techniques alongside an...
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