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By neatly reserving routing resources of an FPGA at design-time, a circuit switching network can be implemented for integrating reconfigurable modules in a two-dimensional manner at run-time. In this network, paths can be set directly by manipulating fractions of the switch matrix configuration. By utilizing disjoint resources for implementing the network and the modules of the system, the network...
In this paper, we demonstrate systems based on Spartan-6 series FPGAs that provide full support for active partial run-time reconfiguration. We will summarize design factors for successfully applying run-time reconfiguration, reveal details on partial reconfiguration on Spartan-6 FPGAs, and introduce our easy to use design flow. In this flow, a module can multiple times be instantiated or even migrated...
In this paper, we show how short-circuits on FPGAs can be caused by partial runtime reconfiguration. Short-circuit can even occur on FPGAs that do not offer any tristate resources just by using off the shelf vendor tools without any bitstream manipulation. The duration of the here presented short-circuits ranges from short spikes up to persistent short-circuits that remain active during runtime. Short-circuits...
This paper analyzes fragmentation issues and proves that the reconfigurable area must be tiled much finer as has been done in existing approaches. The optimal tile grid can typically only be implemented by tiling the reconfigurable area into a two-dimensional grid. This will further increase the utilization of dedicated resources such as block RAMs. In order to provide communication with the reconfigurable...
In this paper, we present the ReCoBus-builder tool chain that simplifies the generation of dynamically reconfigurable systems to almost a push-button process. The generated systems provide one or more resource areas that will be used by different partially reconfigurable modules at runtime. It is possible to integrate multiple partially reconfigurable modules into the same resource area at the same...
In this paper, we present hardware decompression accelerators for bridging the gap between high speed FPGA configuration interfaces and slow configuration memories. We discuss different compression algorithms suitable for a decompression on FPGAs as well as on CPLDs with respect to the achievable compression ratio, throughput, and hardware overhead. This leads to various decompressor implementations...
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