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Modeling of a 1-terminal ESD test setup is described. During the device stress a fast current pulse is forced only through a single pin of a semiconductor device. The model can be used to calculate voltage and current waveforms during the charging and discharging phase of an ESD event which takes place within a few nanoseconds. Charging and discharging of a device depends on the design and dimensions...
An investigation was carried out on the charging voltage of deionized (DI) water during wafer cleaning at wafer sawing process, since it was supposed to be the root cause for EOS damages during semiconductor production. The charging voltage was measured using a non-contact electrostatic field meter. It was found that the positioning of the water filter influenced the amount of charging voltage of...
Charged Device Model (CDM) like stress represents the highest ESD risk during handling of single devices. Today air discharge compromises repeatability of CDM tests of products in a package. The paper demonstrates that the repeatable Capacitive Coupled TLP (CC-TLP) reproduces CDM failure signatures at both package and wafer level. Data will be shown to compare the stress failing level and the failure...
The semiconductor back end manufacturing process starts from the wafer dicing process and finishes with the final tested product with many processes in between where the ESD protection requirement may vary to a great extent. To have an effective ESD control of the different process steps, an ESD protection concept based on S20.20 alone is not sufficient. The control strategy additionally should be...
The demand for ESD control in the semiconductor industry has become more and more stringent especially from customers within the automotive industry segment. The requirement for an ESD capability analysis for the whole manufacturing process line is no longer an option. This paper provides an overview of an ESD capability/risk analysis in a semiconductor back end manufacturing process. The challenges...
Electrical Overstress (EOS) is one of the major complaints from customers in the semiconductor industry. This paper will focus on the area of EOS which is power induced. Some real life examples of cases will be discussed. Practical approaches to identify the root cause in a large manufacturing environment are demonstrated. Long term preventive measures to avoid re-occurrence are proposed.
Nearly all semiconductor devices are stressed according Human Body Model (HBM) and Charged Device Model (CDM) during qualification with a defined current pulse. People in the manufacturing environment are measuring electrostatic voltages on operators, devices, boards or system and try to correlate these values with the robustness values in the datasheets. The paper describes whether this is possible...
The concept of selecting a reduced sample of identical pins for reducing the HBM ESD test times is introduced. It is shown that when the reduced sample has a tight failure distribution above an HBM specification level, the sampling approach can be accurate and will save HBM ESD test time.
Due to downscaling of technology and increase of package size, a reduction in economically achievable CDM robustness of ICs is predicted. The workshop addresses the options and the status of CDM control in manufacturing and testing environments. The necessity of developing more advanced CDM control methods will be discussed. Another question is about the best way for world-wide implementation of advanced...
The ESD protection program set up in the electronics manufacturing facilities especially in China region (evident but not limited to that area) appears to have common weaknesses. They have a lot of ESD protection in place but do not know whether this is the right method at the right place. Nevertheless they have enough backup solutions in place so that they can handle ESDS without big problems. With...
HBM ESD sensitivity testing of high pin count devices is a challenge for current testers and the standardized test procedure. Alternative HBM test procedures are described for the test of devices with fewer tester channels than device pins. Experimental results for the “Split-IO” test method are presented and the risks of divergent results are discussed.
To avoid contamination of wafers, ultra-clean, de-ionized (DI) water is used in the wafer sawing process as a cleaning media and lubricant. There are claims that the high resistivity of DI water creates static charges that cause damaging ESD voltages. Investigations are conducted, and results and conclusions are presented.
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