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In this paper, we propose a dual-edge sense amplifier flip-flop (DE-SAFF) using an improved clocking scheme to reduce area, power, and complexity. The proposed scheme does not require any changes on the single-edge flip-flop to enable dual-edge triggering. The extracted circuit layout of the proposed DE-SAFF has been simulated in TSMC 65-nm technology at a frequency of 2.5 GHz and a throughput of...
In this paper we propose a new approach to balance skew in the clock network by manipulating the operating speed of the flip-flop. Six versions of the master-slave flip-flop with different data to output (TDQ) delays are used in a matched-delay skew compensation technique. The TDQ delay in each version of the flip-flop was increased by increasing the channel length of transistors in intermediate stages...
Portable battery-powered embedded systems necessitate sustainable energy-aware computing. For energy-efficient realization of such systems, static and possibly dynamic optimizations need to be applied to both the hardware and software design abstraction layers. In this paper, models for estimating the energy consumption based on application “activity” are proposed. By “activity” we mean the rate at...
A detailed analytical approach is proposed to determine the required driver strength in the resonant clock generator. The proposed approach reduces area and power overhead by eliminating the need to have switches with programmable widths and reference pulses with programmable duty cycles. Simulation results show accurate estimation of the required driver strength at short pulse widths. However, as...
Resonant clocking is an emerging effective method for reducing power consumption in the clock distribution network. In this technique a resonant (sinusoidal) clock replaces the traditional square wave clock signal. In this paper we combine the emerging resonant clocking technique with the well known dual-edge triggering scheme to enable further power reduction in the clock tree. We propose dual-edge...
Dynamic Voltage Scaling (DVS) is a successful design solution that addresses the challenges associated with low-power/energy and high-performance design in Deep Sub Micron (DSM) CMOS. In DSM, VLSI systems have become interconnect-centric; correspondingly, the associated design solutions should be adapted to preserve their functionality. In reference to this concern, and with respect to DVS, we propose...
A dual-edge sense amplifier flip-flop (DE-SAFF) for resonant clock distribution networks (CDNs) is proposed. The clocking scheme used to enable dual-edge triggering in the proposed SAFF reduces short circuit power by allowing the precharging transistors to be switched on only for a portion of the clock period. The extracted circuit layout of the proposed DE-SAFF has been simulated in STMicroelectronics...
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