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This paper presents a high conversion gain doubler-balanced active frequency doubler for millimeter-wave application. The frequency doubler contains an improved push-push structure, two quarter-wavelength transmission lines, and output power enhancement using negative resistor. The 3-dB band of the frequency doubler is 19∼28 GHz of input frequency, the maximum conversion gain reaches −5.3 dB, the...
A 60 GHz down-conversion mixer used in the unlicensed 60 GHz band system in 65-nm CMOS technology is presented in this paper. Based on the double-balanced Gilbert cell, the mixer comprises a cross-coupled pair to rise conversion gain and two series LCR network resonating at IF frequency to enhance bandwidth. As a result, both high gain and broad bandwidth are achieved. From the simulation results,...
This paper presents a low-voltage and low-power programmable gain amplifier (PGA) for Wireless Sensor Network (WSN) in 0.18 μm CMOS process. MOSFETs biased to moderate inversion region are applied in order to achieve maximum voltage gain, low device dissipation, and high linearity, simultaneously. The proposed PGA consists of three fixed-gain stages and a variable-gain stage. It works at 2 MHz with...
This paper presents an up-conversion mixer for 2.4GHz wireless sensor networks (WSN) in 0.18μm RF CMOS technology. It was based on a double-balanced Gilbert cell type. Operational amplifiers (OP) were used in this design to improve the conversion gain. The performance was verified via simulation using Cadence SpectreRF. The post simulation results indicated that under 1.8V power supply the conversion...
This paper presents a low-voltage and low-power Programmable Gain Amplifier (PGA) designed in a 0.18μm CMOS process, which is applied in Wireless Sensor Network (WSN). To achieve high gain range and linearity performance, multi-stage cascade based on gm-boosted differential pair with degenerated resistor and fully-differential resistive feedback topology is used. AC coupling is utilized to eliminate...
This paper describes a 7-bit 16MS/s CMOS pipeline ADC for the application of ZigBee receiver. A 2.5-bit/stage Multiplying DAC (MDAC) is designed to realize the pipeline ADC. Sample-and-hold amplifier (SHA)-less and operational transconductance amplifier (OTA)-sharing technique is adopted to save power dissipation. Dynamic comparator can be chosen to reduce the power dissipation. Designed in a TSMC...
This paper presents a wideband low noise IF amplifier developed for the ALMA Front End system using 90nm CMOS. A topology of shunt-series peaking and active shunt feedback low noise IF amplifier is proposed to extend the 3-dB and input matching bandwidth, combined with a series input inductor. The circuit achieves a flat gain of 34dB, while the 3-dB bandwidth as well as return loss of better than...
A 5-GHz CMOS programmable frequency divider is presented in this paper, whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications. The divider has two blocks, a dual-modulus prescaler (DMP) integrating a frequency halving circuit, and a pulse-swallow counter. In the DMP, an improved phase switching technique is used to reduce the power consumption. Designed in 0.18-µm CMOS process,...
A 10-Gb/s inductorless limiting amplifier for optic-fiber transmission system is designed and fabricated in a 0.18-μm CMOS technology. The whole circuit consists of an input buffer, three broadband gain stages, an output buffer for driving 50-Ω transmission lines and a DC offset cancellation circuit. By employing a third-order interleaving active feedback, the bandwidth of the proposed circuit can...
A 12-channal 120-Gb/s optical receiver front-end amplifier array has been designed in a 0.18-μm CMOS process. This front-end amplifier array incorporates transimpedance amplifiers (TIAs) and limiting amplifiers (LAs). A regulated cascode (RGC) input structure, active inductor peaking and feedback technique are exploited to enhance the bandwidth without deterioration of the other performances. And...
This paper presents a low-power low-IF RF frontend for 2.4GHz wireless sensor networks (WSN) in 0.18μm RF CMOS technology. The RF frontend consists of a variable gain low noise amplifier (VG-LNA), a quadrature passive mixer and a divide-by-two circuit which generates the differential quadrature LO signals for quadrature balanced mixer. The effect of the input parasitic capacitance on the inductively...
A 40-Gb/s integrated parallel optical receiver front-end amplifier for VSR (very short reach) optical fiber transmission systems has been developed. It was designed and fabricated in a 0.18-mum CMOS technology and consists of 12 channels in parallel with a data rate of 3.318-Gb/s in each channel. A regulated-cascode (RGC) structure and noise optimization were used in the design of transimpedance amplifier...
A 3.33 GHz-3.53 GHz power amplifier for satellite communications is designed by using JAZZ 0.35 ??m SiGe BiCMOS process. This power amplifier works in class AB type with single-ended structure. With a supply voltage of 3.3 V, the power gain is 23 dB at its center operation frequency and it can transmit 29.98 dBm output power to a 50 ?? load at 1 dB power compression point with 33.84% power added efficiency...
This paper describes a wideband variable gain LNA for multi-standard wireless LAN operating in the frequency bands of 4.9-5.825 GHz, including three standards: IEEE 802.11a, ETSI HiperLAN2 and MMAC HiSWANa. By using a simple feedback loop at the second stage of LNA we realized the continuous gain control. A variable gain range of 18.7 dB (0.7 dB to 19.4 dB) is achieved. The noise figure is 1.1 dB...
A 4 GHz quadrature voltage-controlled oscillator (QVCO) topology is proposed where a planar spiral transformer is used as coupling terminals. Two identical LC oscillators are cross-coupled by the transformer to generate the quadrature outputs. The transformer also serves as filtering network for the oscillators to improve the phase noise performance. The quadrature oscillator based on the proposed...
In this paper, a 10 GHz VCO (voltage controlled oscillator) based on 0.35 um SiGe BiCMOS technology is presented. It is designed for 10 Gb/s CRC (clock recovery circuit) in optical communication systems and X band wireless applications. Cross coupled differential topology is adopted. It can operate from 9.78 GHz to 10.35 GHz with a phase noise of -106 dBc/Hz at 1 MHz offset. For the 1.8 V supply voltage,...
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