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3D-TCAD simulations in a 0.18um process are used to show the effect of gate shapes on the single event transients of both PMOS and NMOS. The results turn out that the SET pulse widths of enclosed layout transistors are much smaller than the standard layout transistors. The mechanisms and process that affect the charge collection of different layout structures are studied. Ssuggestions are made towards...
In order to advance the performance of the ESD circuit for the power rail protection, a kind of design scheme named GDNMOS (Gate Driven NMOS) is studied in this paper. NMOS, inverter and RC couple cell are the makeup in this scheme. Device simulation in a pre_Si phase will be an economical way. NMOS parameters are optimized in a device simulation way firstly. By discharge time study the RC-time is...
In this paper a kind of ESD protection design scheme named GDNMOS (gate driven NMOS) is investigated. GDNMOS is used more and more wildly for its excellent performance in submicron CMOS VLSI ESD protection. NMOS, inverter and the RC couple cell are the makeup in this scheme. ESD device simulation in order to evaluate the robustness of the ESD protection device is performed firstly. Device simulation...
Three-dimensional simulation is used to explore the new charge-collection mechanisms in highly-scaled MOSEFT. The results show the charge collection with the parasitic bipolar conduction can cause an increased SEU sensitivity. Then the problem of multiple-node upset in a 0.18 mum DICE cell is studied .The results show not only the transient floating node and charge lateral diffusion are the key reasons...
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