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This paper describes fault tolerance techniques which have been developed and implemented for the multiprocessor system DIRMU 25 — a 25-processor system which is operational at the University of Erlangen-Nuremberg. First a short overview of the DIRMU hardware architecture, programming environment and parallel application programs is given. Fault-diagnosis and reconfiguration are implemented in a layer...
This paper presents two approaches to pattern based exploration and mapping of large scale, maze-like environments. These approaches fit the needs of single robot as well as multi-robot exploration. A further aspect is the subsequent localization of participating robots within previously generated maps. The construction of these maps relies mostly on the extraction and merging of environmental describing...
A robust swarm intelligence based approach for the self-reconfiguration of a fault-tolerant multi-legged walking robot is elaborated in this paper. It is used to reconfigure the posture of the legs of the robot after some failure has occurred within the robotpsilas legs and it is based on the intrinsic properties seen within swarms and boids in nature. The reconfiguration method presented does not...
Traditional design of network processors is complicated by two conflicting demands, flexibility and performance. On the one side, network processors should be flexible enough to adapt to changing protocols and varying traffic profiles, on the other side they have to cope with increasing data rates of network links. This demonstrator shows that runtime reconfigurable systems have the potential to optimise...
This paper explores the design space for runtime reconfigurable systems. A broad range of systems is surveyed and a set of parameters applicable for characterizing runtime reconfigurable systems is proposed. Compared to other surveys the focus is set on the system architecture, not on the underlying hardware structure. This allows a discussion that primarily considers the actual motivation for utilising...
This paper presents an architectural framework and simulation model for tile-based runtime reconflgurable systems. The framework accounts for all hardware limitations of actual FPGA devices and is based on the division of the reconflgurable system partition into a set of small tiles. These tiles can either be exchanged individually at runtime or can be grouped to larger tiles and be exchanged as a...
A hybrid compute system (HCS) combines standard CPUs and reconfigurable devices, usually FPGAs, in one system. These systems have become more attractive again, due to a closer and hence faster coupling of both computational components. From our work with several designs for the same application, we have found the communication between a CPU and a FPGA-based coprocessor to relate either to pipelining...
Growing bandwidth of network connections as well as strong progress in network protocols and new applications require efficient and flexible network hardware. Network processors are applied for packet processing in routers and gateways. Unfortunately, deep-packet processing tasks lack the support of dedicated co-processors. Because of numerous time-consuming algorithms required, a dynamically re-...
In this paper we present an implementation of a Reed/Solomon (R/S) coprocessor to be used on a hybrid computing system, which combines general purpose CPUs with FPGAs. The coprocessor accelerates the encoding of user data to be stored block-wise on a distributed, failure tolerant storage system. We document design constraints and their impact on the resulting architecture. Measurements are presented...
This paper describes a lightweight framework for prototyping runtime reconfigurable systems in a Xilinx Virtex-II Pro FPGA. The framework provides a reconfiguration and control infrastructure that allows components of the prototype system to be modified or exchanged at runtime by means of partial reconfiguration of the FPGA. The system state may be monitored and influenced by a programmable controller...
This paper gives a survey of communication architectures which allow for dynamically exchangeable hardware modules. Four different architectures are compared in terms of reconfiguration capabilities, performance, flexibility and hardware requirements. A set of parameters for the classification of the different communication architectures is presented and the pro and cons of each architecture are elaborated...
This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor for offloading computationally intensive tasks from a network processor. The system-on-chip architecture is based on an adaptable network-on-chip which allows the dynamic replacement of hardware modules as well as the adaptation...
This paper presents an intra-node Route Discovery Protocol (RDP) applicable to multistage switch fabrics in nodes of ATM Local Area Networks (LANs), as well as in transit nodes of future high-speed Metropolitan or Wide Area Networks (MANs or WANs). The proposed RDP automatically builds and periodically updates routing tables in each network adapter. These routing tables contain the mapping between...
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