The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Motivations for three-dimensional (3D) integration include reduction in system size, interconnect delay, power dissipation and enabling hyper-integration of chips fabricated using disparate process technologies. Although various low-power commercial products exploit the advantages of improved performance and increased device packing density realized by 3D stacking of chips (using wirebonds), such...
Compact physical models are derived for predicting power supply noise of chips in the gigascale integration (GSI) era. These models consider both IR-drop and simultaneous switching noise (SSN) and give a quick full waveform description of the first droop power supply noise as well as its peak value. The derivation of these models proceeds by considering a frequency domain representation of power grids...
Sea of Leads (SoL) is an ultrahigh I/O density (>10/sup 4/ leads per cm/sup 2/) compliant wafer level package (CWLP) that potentially enables terabit on/off chip electrical bandwidth as well as enhances on-chip high current (e.g. >290 A) distribution of a mixed-signal system-on-a-chip (SoC). The addition of embedded air-gaps may mitigate problems with thermal expansion between the chip and printed...
IR-drop and simultaneous switching noise (SSN) are the main concerns for the design of an on-chip power distribution network. Analytical models for IR-drop and SSN in an on-chip power distribution network are presented. These models are used to design an optimum power distribution network to meet the requirements for the system. Utilizing the methodology presented, the requirements for power distribution...
A global interconnect design window for a three-dimensional system-on-a-chip (3D-SoC) is established by evaluating the constraints of 1) wiring area, 2) clock wiring bandwidth, and 3) crosstalk noise. This window elucidates the optimum 3D-SoC global interconnect parameters for minimum pitch, minimum aspect ratio, or maximum clock frequency. In comparison to a two-dimensional system-on-a-chip (2D-SoC),...
Via blockage due to signal interconnects and its impact on wirability of multi-billion-transistor chips are systematically analyzed. Via classifications are introduced. By taking advantage of a stochastic interconnect length distribution and a multi-level interconnect network architecture, a physical via blockage model exploiting channel availability is proposed. This model reveals that the most severe...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.