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The mismatch of current sources is caused by the circuit error and the process variation. Introducing the channel length modulation λ to the Pelgrom model for variation analysis, we describe a new ΔI/I model of current sources. To make it clear what variation parameter influences the mismatch, we implemented a test chip on 90nm process technology, where we can collect the characteristics variation...
This paper addresses the problem of transistor decomposition, which can be used in high accuracy analog applications and structured analog design. We made a test chip to verify the feasibility of the transistor decomposition because of the lack of theoretical support. The DC/AC measurement results from the chip suggests that the decomposition, the transistor channel tuning, as well as structured analog...
Size of STI wells is another significant factor to affect the stress magnitude (device mobility) besides size of transistor active regions. In this paper, we present a technique for improving device mobility in the critical path via global STI well width adjusting following the chip placement stage. The methodology formulates the original device mobility enhancement problem as a series of convex geometric...
This paper presents a novel regularity evaluation of placement structure and MOS analog specific layout techniques called diffusion sharing and well island generation, which are developed based on sequence-pair. The regular structures such as topological row, array and repetitive structure are characterized by the way of forming subsequences of a sequence-pair. A placement objective is formulated...
For analog circuits, the current source is one of the most essential functions, and variation of its characteristic seriously influences to the accuracy of the performance. This paper presents a new methodology for analyzing the layout dependency of the variation of the current source transistor. We employ a current-driven D-A converter to investigate the dependency of the current source upon the...
This paper aims at developing a transistor-level programmable technology which is composed of two key mechanisms; One is that a MOS transistor is divided into sub-transistors connected in parallel, so that the transistor behaves various characteristics by switching the parallel connection. The other mechanism changes Vth and gm of the transistor by adjusting the bulk potential based on body effect...
This paper addresses the problem of optimizing metallization patterns of back-end connections for the DMOS based driver since the back-end connections trend to dominate the overall on-resistance Ron. We propose a heuristic algorithm to seek for better shapes for the patterns targeting at minimizing Ron and at balancing the current distribution. In order to speed up the analysis, the equivalent resistance...
In analog circuits, blocks need to be placed symmetrically to satisfy the devices matching. Different from the existing constraint-driven approaches, the proposed topological symmetry structure enables us to generate a symmetrical placement without any constraint. Simulated annealing is utilized as the framework of the optimization, and we propose new move operation to maintain the placement's topological...
This paper introduces a new concept of floorplanning and block placement, called structured placement. Regularity is a key criterion of structured placement so that placement can make progress beyond constraint-driven approaches. This paper formulates the topological regularity that is extractable from a sequence-pair. Regular structures like arrays and rows are defined on a single-sequence that is...
Equi-length constraints are widely used for a substitution for IR-drop or skew constraints. This paper provides a linear programming formulation for compaction with equi-length constraints, where the authors make use of multi-SP that is an extension of sequence-pair to multi-layer layouts. Since multi-SP stores horizontal relations and vertical ones among modules and wires in the same data structure,...
Analog layout automation is one of the most challenging subjects that has to cope with trade-offs among analog specific requirements such as noise, linearity, gain, supply-voltage, speed, power consumption, etc. This paper proposes a novel porting methodology that guides the reuse of analog IPs, followed by an automation system. The methodology introduces a concept of conservative properties that...
In module generation for analog cell layout, it is necessary to incorporate the designers' empirical techniques to achieve small area as well as high performance. This paper presents the formulation of two types of module generation problems, faithful to expert's empirical knowledge, to ease such incorporation. One is series module generation problem, where we introduce equivalent circuit modifications...
In analog layout, the placement and routing are closely connected with each other in the optimization of the area, the parasitics, the mutability and so on. In this paper, we introduce a common data-structure to the placement and multilayer routing, where devices and wires are represented by united rectangles. It is called multi-layer sequence-pair (multi-SP). We also provide a bi-directional translation...
Given a route which connects terminals on a one-layer routing area (Steiner tree), flip is a procedure that makes a current route change its configuration within its peripheral domain. A flip reforms a route by replacing one of its edges with a minimal detour. A route can flip one nearby obstacle. If the obstacle is another route, a more organized operation, called the dual flip, is applied to a pair...
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