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This paper presents a MICS/ISM band receiver for ultra-low-power applications with a passive RF front-end. A shunt passive mixer along with low input capacitance amplifiers is introduced to decrease the large load capacitor and minimize power consumption of the Local Oscillator (LO) buffers without significant noise figure (NF) degradation. Measurement results show that the receiver consumes 89 μW...
A buck DC-DC converter with very high light load efficiency is presented in this paper. It introduces hysteretic control when the large output ripple problem is not critical, especially in light-load condition. Moreover, a fast-response zero current detector (ZCD) is adopted to make the converter work in discontinuous conduction mode (DCM). Due to hysteretic control extremely simplified the control...
A novel architecture of high frequency resolution LC-tank based digitally controlled oscillator (DCO) is presented in this paper. The proposed architecture utilizes a differential tapped inductor and a capacitor array within the taps for fine frequency tuning. A prototype of 1.6 GHz DCO integrated in 0.18-μm CMOS technology exhibits a tuning range of 40.2% and a phase noise of −123.6 dBc/Hz@1MHz....
A wide band radio frequency (RF) root-mean-square (RMS) power detector (PD) is presented in this paper. A CMOS rectifier with unbalanced source-coupled pairs and auxiliary capacitors is utilized to constitute the reverse received signal strength indicator (reverse-RSSI) architecture as proposed power detector with operating frequency from 300 MHz to 10 GHz. The auxiliary capacitors are introduced...
This paper presents a CMOS RF tunable 4th-order active bandpass filter with the proposed inductor-less biquads. The NMOS cross-coupled pair is utilized in the biquad for the positive-feedback to form the complex pole, which enables the filter working at high frequency of 5GHz with low power of only 4.8mW from 1.2V power supply. Due to the inductor-less topology, the proposed filter only occupies 0...
This letter proposes a miniature CMOS stacked spiral-coupled (SSC) directional coupler for a fully integrated CMOS transceiver to isolate the large transmit power from the transmitter to the receiver. It consists of two 90 -rotated center-aligned SSC coils. The path center of one coil is aligned to the gap center of the other coil. The grounded secondary coil plays a role of ground shielding...
A CMOS phase-locked loop (PLL) which synthesizes frequencies between 474 and 858 MHz in steps of 1 MHz and settles in less than 180 ??s is presented. This PLL can be implemented as a sub-circuit for a frequency synthesizer which serves for UHF Digital-TV receiver. To realize fast loop settling, integer-N architecture that work with 1 MHz reference frequency is implemented and a novel adaptive frequency...
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